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Sarvesh Kumar Prajapati

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Aug 2026

Design of SOI Strained-Silicon I-MOS Architecture for Low-Voltage Snapback Zero-Capacitor 1T-DRAM

This paper presents a design and reliability analysis of a 1-Transistor (1-T) Zero Capacitor (0-C) dynamic random access memory (DRAM) cell utilizing an impact-ionization metal oxide semiconductor field-effect transistor (I-MOS) architecture with a novel strain configuration comprising a strained-silicon channel and co...

Sarvesh Kumar Prajapati, Vikram Sharma, Pragati Singh · 0 citations

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