Design of SOI Strained-Silicon I-MOS Architecture for Low-Voltage Snapback Zero-Capacitor 1T-DRAM

Abstract

This paper presents a design and reliability analysis of a 1-Transistor (1-T) Zero Capacitor (0-C) dynamic random access memory (DRAM) cell utilizing an impact-ionization metal oxide semiconductor field-effect transistor (I-MOS) architecture with a novel strain configuration comprising a strained-silicon channel and conventional silicon source/drain regions. The suggested strained-silicon bipolar I-MOS for the realization of a 1T zero-capacitor DRAM device functions as a floating region and is used to store holes for the application of capacitorless 1T DRAM. High-impact ionization at the channel-drain junction is the main cause of the holes. As a result, there is less capacitive coupling between the body, gate, and channel regions. By optimizing the gate work function to 4.5 eV and leveraging the strain-induced bandgap narrowing $\left(\Delta E_{g}\right)$ within the channel, the device achieves superior carrier mobility and enhanced impact-ionization rates. Numerical analysis reveals a significant reduction in the critical avalanche breakdown voltage $\left(V_{D S}\right)$ to 1.61 V, addition according Fig. 6 proposed device drain voltages lower $\left(\left(V_{L D}\right)=0.45 \mathrm{V}\right. \text{to} \left(V_{L U}\right)=0.8 \mathrm{V}$) marking a distinct improvement over the 2.81 V and 1.86 V limit seen in existing GAA ARCH TFET and SiGe I-MOS baselines, the suppression of localized Shockley-Read-Hall (SRH) generation and the optimization of Band-to-Band Tunneling (BTBT) current transport significantly boost the cell's sensing margin. The proposed 1-T Zero capacitor DRAM demonstrates non-destructive reading and exceptional long-term endurance. This research presents promising results for future DRAM design using deep nanometre technology.