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Sophia Silveira

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Open access Sep 2026

RS5V-SoC: Architecture and ASIC Design of a Vector-Enabled RISC-V SoC

It is demonstrated that for embedded workloads, a 4-lane, 128-bit vector unit with a 32-bit bus offers the best area-performance trade-off, and a design-space exploration of the vector unit is presented.

F. Moraes, Antonio Ribeiro Dos-Santos, Lucas Damo et al. · 0 citations

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