RS5V-SoC: Architecture and ASIC Design of a Vector-Enabled RISC-V SoC
TL;DR
It is demonstrated that for embedded workloads, a 4-lane, 128-bit vector unit with a 32-bit bus offers the best area-performance trade-off, and a design-space exploration of the vector unit is presented.
Abstract
Systems-on-Chip (SoC) using the RISC-V Instruction Set Architecture (ISA) play a central role in the development of embedded systems by enabling flexibility, extensibility, and low power consumption. This SoC, submitted to tape-out in the context of the SBMicro-APCI 2025 call, presents the RS5V-SoC, which integrates custom peripherals, RISC-V ISA extensions for cryptographic (AES) and vector processing, and support for the Zephyr RTOS. The vector processing extension accelerates data-parallel kernels, such as those commonly used in machine learning applications. This paper has two main objectives. First, it presents the RS5V-SoC architecture and a design-space exploration of the vector unit. We demonstrate that for embedded workloads, a 4-lane, 128-bit vector unit with a 32-bit bus offers the best area-performance trade-off. Second, it details the ASIC implementation of the RS5V-SoC in a 65 nm CMOS technology, describing each step of the design flow, from floorplanning to metal fill, the final step prior to tape-out. The design is validated through an FPGA-to-ASIC flow and targets embedded applications, such as Internet of Things devices and machine learning. The processor is publicly available at https://github.com/gaph-pucrs/RS5.