Thirumalaiswamy V.

Branch-Free Binary128 Multiplication: SRMA Implementation with SSE2 Instructions and Kintex-7 Validation

This research presents an optimized, reduced-clock-cycle approach for performing 128-bit floating-point calculations on Field-Programmable Gate Arrays (FPGAs) using the SRMA architecture, which not only reduces execution time but also decreases energy consumption on Kintex-7 FPGA boards.