Branch-Free Binary128 Multiplication: SRMA Implementation with SSE2 Instructions and Kintex-7 Validation
TL;DR
This research presents an optimized, reduced-clock-cycle approach for performing 128-bit floating-point calculations on Field-Programmable Gate Arrays (FPGAs) using the SRMA architecture, which not only reduces execution time but also decreases energy consumption on Kintex-7 FPGA boards.
Abstract
In the modern world, 128-bit binary arithmetic is essential for achieving high numerical accuracy but remains expensive to implement in processors. This research presents an optimized, reduced-clock-cycle approach for performing 128-bit floating-point calculations on Field-Programmable Gate Arrays (FPGAs) using the SRMA architecture. The SRMA-focused implementation not only reduces execution time but also decreases energy consumption on Kintex-7 FPGA boards. Yet, today most of the processors are x86-64 CPU's which don't support floating point 128-bit calculations natively. On high performance processors, these generic methods trigger delayed pipelines and branch mispredictions, leading to longer clock cycles and increased energy. To unlock a processor's full potential, bridging the gap between slow software emulation and hardware support is a necessary task. The SRMA algorithm works on mantissa computations where it handles the branch-free arithmetics, where traditionally Generic algorithms use heavy branch-pipelining leading to unnecessary clock-cycles. This approach highlights the split-mantissa, an advanced approach where the mantissa of the scientific computations are split accordingly and then appended for minimal error. There is a bottleneck where software uses generic code that ignores the strengths of modern CPUs. Our ultimate goal is to run at speeds that make it practical for scientific computing at lower cost.