Design of a 32-Bit RISC-V Processor with Dynamic Floating-Point ALU Switching

Abstract

This project focuses on designing and simulating a 32-bit RISC-V processor that can switch dynamically between an Integer ALU (RV32I) and a Floating Point ALU (RV32F). The main aim of the work is to make the processor to perform both integer and floating-point operations using a single architecture, which eliminate the need for separate designs. The two ALUs receive the same input values, and a multiplexer inside will select the correct output depending on the type of operation. The entire design is written in Verilog/SystemVerilog and is tested using behavioral simulation in Xilinx Vivado. The simulation results show the correct outputs for both integer and IEEE-754 floatingpoint arithmetic, proving that the switching mechanism works smoothly without any error. The processor uses a simple, nonpipelined structure, making it easy to understand and also it is suitable for academic learning, research practice, and future development. This model also provide a strong base for upcoming improvements such as adding pipeline stages, hazard detection, etc.