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Author

Thockchom Birjit Singha

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Sep 2026

Low-Overhead Power Side-Channel Resistant AES Accelerator for RISC-V via Stall-Induced Trace Desynchronization and Activity Equalization

The rapid proliferation of Internet-of-Things (IoT) applications has increased the demand for secure and efficient cryptographic processing in resource-constrained System-on-Chips (SoCs). This brief presents a compact and hardware-efficient Advanced Encryption Standard (AES) accelerator for RISC-V (RISCY) processors, i...

Anupam Kumari, Titu Mary Ignatius, Thockchom Birjit Singha et al. · 0 citations

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