Low-Overhead Power Side-Channel Resistant AES Accelerator for RISC-V via Stall-Induced Trace Desynchronization and Activity Equalization

Abstract

The rapid proliferation of Internet-of-Things (IoT) applications has increased the demand for secure and efficient cryptographic processing in resource-constrained System-on-Chips (SoCs). This brief presents a compact and hardware-efficient Advanced Encryption Standard (AES) accelerator for RISC-V (RISCY) processors, integrated with a lightweight digital power-side-channel countermeasure. The proposed approach combines stall-induced trace desynchronization and activity equalization to disrupt power trace alignment and mitigate power attacks without relying on hardware-intensive techniques. The proposed design incurs ultra-low hardware overhead of only 0.27%/1.27% in area and 0.23%/−4.19% in power for the system/AES implementations, respectively, while preserving the critical-path delay. Security evaluation demonstrates strong leakage suppression, achieving Measurements to Disclosure (MTD) greater than 1 million, reducing the Signal-to-Noise Ratio (SNR) to $0.518~(\lt 1)$ , maintaining Mutual Information (MI) in the milli-range, and satisfying the Test Vector Leakage Assessment (TVLA) criterion within the ±4.5 threshold. The proposed digital co-design provides a practical, low-overhead solution for secure AES acceleration in lightweight IoT platforms.