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Review Open access Sep 2026

Design of 8-Bits Fast Multiplier to optimize constraints

High speed multiplication has always been a fundamental requirement of high performance processors and systems. With MOS scaling and technological advances there is a need for design and development of high speed data path operators such as adders and multipliers to perform signal processing operations at very high spe...

V. G, Bharathi Gururaj · 0 citations
Review Open access Aug 2026

A Survey of AES-256 and SHA-256 Hardware Architectures on FPGA

It can be deduced that an efficient resource usage, scalability and secure hardware implementation is possible by integrating the AES-256 and SHA-256 components into a modular FPGA architecture.

V. G, Bharathi Gururaj, Mruthika N. et al. · 0 citations

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