A Survey of AES-256 and SHA-256 Hardware Architectures on FPGA
TL;DR
It can be deduced that an efficient resource usage, scalability and secure hardware implementation is possible by integrating the AES-256 and SHA-256 components into a modular FPGA architecture.
Abstract
In the present day, data confidentiality and integrity are among the major concerns in the embedded and communication systems and hardware-based cryptographic systems are playing a significant role in this regard. Moreover, the flexible features of FPGA implementations of cryptographic algorithms, such as greater performance, higher parallelism, and greater protection for sensitive data, are better than software-based approaches. This survey discusses the latest FPGA-based architectures of the AES-256 and the SHA-256, along with the design methodologies, optimization techniques and integration strategies. An analysis of existing studies is conducted to understand the pros and cons of various architectures, resource usage, throughput and implementation methods. The survey reveals that most current designs focus on optimizing only one aspect of encryption and hashing separately, whereas integrated designs may require extra hardware because of the duplicated control and interface logic. From these observations, it can be deduced that an efficient resource usage, scalability and secure hardware implementation is possible by integrating the AES-256 and SHA-256 components into a modular FPGA architecture.