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Wen-Wu Liu

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Conference Aug 2026

A Tester on Chip (ToC) integrated Embedded Logic Analyzer for DRAM SLT real-time Failure Capture and Diagnosis

This paper presents an integrated Tester on Chip (ToC) architecture supporting high-speed exceeding 8Gbps for DDR4/5 and LPDDR4/5 across both component and module levels based on simulation. The proposed design independently implements System Level Test (SLT) and Automatic Test Equipment (ATE) test functions within a s...

Li Ding, Chris Eom, Jun-Lin Yang et al. · 0 citations

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