A Tester on Chip (ToC) integrated Embedded Logic Analyzer for DRAM SLT real-time Failure Capture and Diagnosis

Abstract

This paper presents an integrated Tester on Chip (ToC) architecture supporting high-speed exceeding 8Gbps for DDR4/5 and LPDDR4/5 across both component and module levels based on simulation. The proposed design independently implements System Level Test (SLT) and Automatic Test Equipment (ATE) test functions within a single chip and establishes an internal data path through a dedicated Embedded Logic Analyzer (ELA) to address the lack of failure pattern visualizing in conventional structures. Furthermore, the architecture is designed to support multiple failure trigger conditions, such as DQ signals, timing or protocol violation, enabling precise on-chip failure analysis without the requirement for external logic analyzers. By capturing complex system-level failures in real-time and enabling immediate reproduction in the ATE environment, this approach achieves a significant reduction in debug turn-around time (TAT) and maximizes overall diagnostic efficiency. The ToC is fabricated in 12nm logic process.