reinforcement learning

Reproducibility archive for Target-Scale Sensitivity in Adaptive Pessimism for Tabular Offline Reinforcement Learning: An EdNet-KT4 Study

This archive accompanies the manuscript "Target-Scale Sensitivity in Adaptive Pessimism for Tabular Offline Reinforcement Learning: An EdNet-KT4 Study." It contains the analysis code, frozen experimental protocol, primary clean-200k results, and sensitivity-analysis results needed to reproduce the reported tables and f...

Adaptive Terrain Traversal: A Model-Free Reinforcement Learning Approach to Lunar Rover Active Suspension System

Velocity adaptive preview path tracking control for autonomous vehicles using deep reinforcement learning with Lyapunov function-based reward shaping

Traditional rule-based path tracking controllers of autonomous vehicles (AVs) often struggle with nonlinear vehicle dynamics, parameter tuning, and changes in road conditions. Learning-based methods partly address these issues, but remain limited in adapting to velocity changes, exploiting the preview information from...

Deep Q-Network-Assisted Energy-Aware Scheduling Framework (DQN-EAS) for Scientific Workflows

In modern computing environments, scientific workflows play a vital role in orchestrating complex computational tasks across diverse resources and domains. As high-performance computing (HPC) systems continue to evolve, the need for energy-efficient scheduling methods — without compromising task completion time — has b...

Artificial Intelligence in CPU and ASIC Design: Applications, Design-Space Exploration, and Engineering Constraints

Modern CPU and application-specific integrated circuit (ASIC) development requires engineers to search large design spaces while satisfying power, performance, area, timing, and correctness constraints. Artificial intelligence (AI) is increasingly being integrated into electronic design automation (EDA) to accelerate p...

Cache-Fused Kinematic Rails: Ex-Ante Silicon Alignment via In-Vivo KV-Cache Metric Grafting

Abstract of Cache-Fused Kinematic Rails: Ex-Ante Silicon Alignment via In-Vivo KV-Cache Metric Grafting Current Large Language Model (LLM) alignment relies primarily on post-hoc, output-level correction mechanisms such as external API meta-governors, Reinforcement Learning from Human Feedback (RLHF), or post-generation...

Artificial Intelligence in CPU and ASIC Design: Applications, Design-Space Exploration, and Engineering Constraints

Modern CPU and application-specific integrated circuit (ASIC) development requires engineers to search large design spaces while satisfying power, performance, area, timing, and correctness constraints. Artificial intelligence (AI) is increasingly being integrated into electronic design automation (EDA) to accelerate p...

Performance and Hardware Complexity Analysis of Ripple-Carry and Carry-Lookahead Adders for Logic Synthesis Optimization

As integrated circuit fabrication approaches physical limits, classical Electronic Design Automation (EDA) algorithms struggle with high-dimensional search spaces during multi-objective Power, Performance, and Area (PPA) optimization. Binary addition circuits form the core bottleneck of arithmetic processing units; thu...

Machine Learning in Industrial Logic Gate Synthesis: Operational Capabilities and Verification Constraints

AbstractProgrammable Logic Controllers (PLCs) rely on fixed-threshold comparators that frequently trigger false emergency trips when exposed to electromagnetic interference, thermal drift, and mechanical vibrations. This paper evaluates applying machine learning to industrial logic gate synthesis, using Graph Neural Ne...

AI-Augmented Logic Synthesis for Edge-Deployed Swimmer Detection Systems

Vision-based swimmer and drowning detection systems, built primarily on lightweight YOLO architectures, have achieved measurable gains in accuracy while shrinking model size for resource-constrained edge hardware. However, Field-Programmable Gate Array (FPGA) accelerators hosting these models continue to rely on conven...

Machine Learning in Industrial Logic Gate Synthesis: Operational Capabilities and Verification Constraints

AbstractProgrammable Logic Controllers (PLCs) rely on fixed-threshold comparators that frequently trigger false emergency trips when exposed to electromagnetic interference, thermal drift, and mechanical vibrations. This paper evaluates applying machine learning to industrial logic gate synthesis, using Graph Neural Ne...

Performance and Hardware Complexity Analysis of Ripple-Carry and Carry-Lookahead Adders for Logic Synthesis Optimization

As integrated circuit fabrication approaches physical limits, classical Electronic Design Automation (EDA) algorithms struggle with high-dimensional search spaces during multi-objective Power, Performance, and Area (PPA) optimization. Binary addition circuits form the core bottleneck of arithmetic processing units; thu...