Sep 2026· IEEE Journal of Solid-State Circuits· Vol 61, pp. 5125-5141· 0 citations· 64 references
Abstract
We present PROTEUS, an 18 mm2 programmable general-purpose digital compute-in-memory (GP-DCIM) accelerator integrating 4 Mb resistive random access memory (RRAM) and 2.6 Mb tensor static random access memory (SRAM) with a 32-bit hierarchical DCIM instruction set architecture (ISA). PROTEUS features fine-grained 1-D matrix tiling and a reconfigurable DCIM datapath/pipeline for near-100% memory utilization, supporting INT8/INT16/FP8/FP16 DCIM computations. PROTEUS unifies SRAM/RRAM dataflows and embeds nonvolatile micro-programs in RRAM to enable rapid switching among prestored kernels without incurring off-chip instruction feeds or RRAM rewrites. Fabricated in 40 nm ultra-low power (ULP) CMOS with foundry RRAM, PROTEUS delivers 702 GOPS throughput, 6.4 TOPS/W energy efficiency, and 0.039 TOPS/mm2 compute density. It is validated on ResNet-20, BERT-Tiny, MobileViT, GraphSAGE, and Vision Mamba, demonstrating versatility across CNN, Transformer, hybrid CNN-Transformer, graph neural network (GNN), and state-space model (SSM) workloads.
The rise in edge computing, and domain-specific workloads, necessitates the development of hardware acceleration with increased flexibility and lower latency that will be tightly coupled to open-source processor cores. In this paper, we explore the design and bare-metal implementation of a RISC-V SoC comprising a PicoRV32 scalar core and two memory-mapped hardware accelerators: FPSQRT core and a reconfigurable CRC-32 integrity engine. Using a customized three-state AXI4-Lite FSM-based interface, our design effectively separates the acceleration compute latency from that of the bus timings enabling bare-metal firmware to perform its coprocessor computations without OS intervention. Simulation results show performance speed-ups of 1.96x and 9x for the FPSQRT and CRC-32 respectively giving a total speedup of 12x relative to software only. Post-implementation synthesis on the Xilinx Zynq-7000 family FPGA (XC7Z020) shows full timing closure at a clock frequency of 100 MHz with WNS of +7.058 ns. Resource utilization figures are exceptionally low with the design requiring only 5,208 Slice LUT (9.8%), and 11.4% of block RAM with total on-chip power dissipation of 1.694 W. Our hardware-in-the-loop test on the Digilent ZedBoard confirmed the functional accuracy and operational stability with bare-metal operation status confirmed by LED (T21, T22) and a serial console.
P.anuradha, Vulapala Tejashwi, Meenugu Venkateshwarlu et al.· 2026 7th International Confe...· 0 citations
Compute-in-Memory (CIM) based on resistive random access memory (RRAM) offers significant advantages in energy efficiency and parallelism, making it a promising solution for accelerating neural networks. However, the computational accuracy, energy efficiency, and flexibility of current CIM chips are still challenged by practical issues such as device and circuit-level non-ideality and the high overhead of peripheral circuits, which remain inadequately addressed in existing designs. To address these challenges, this work proposes REF-CIM, a 40nm robust, energy efficient and flexible RRAM- CIM macro that achieves non-ideality tolerance, high energy efficiency and configurable precision, featuring: 1) a complementary multi-bit input unit (CMIU) with symmetric bit-line access; 2) a proportional current-scaling clamp circuit (PCSC); 3) a distributed tree-based sparse analog-to-digital converter (DTS-ADC); and 4) a configurable multi-mode deployment scheme for supporting diverse neural network precisions. The performance of the proposed macro is evaluated through chip measurements, considering non-ideal effects such as IR-drop, device variation, and analog circuit noise. Simulation results calibrated with measurement data demonstrate a peak energy efficiency of 29.1 TOPS/W@8bIN/8bW/16bOUT, with classification accuracy reaching 92% on the CIFAR-10 dataset under 10% device variation.
H. Ding, Yunfan Yang, Zongwei Wang et al.· IEEE Transactions on Circuit...· 0 citations
Embedded systems increasingly require on-device deep learning, yet their processors must simultaneously handle real-time sensing, networking administration, and data control. Existing Field-Programmable Gate Array (FPGA) accelerators typically target peak per-operator throughput without addressing concurrent execution demands of real-time embedded platforms. This paper presents a systolic array-based accelerator prototype implemented on the Zynq-7000 SoC integrated directly into PyTorch, enabling dense linear algebra to be delegated to the FPGA chip while Cortex-A9 continues executing the software stack uninterrupted. Unlike traditional accelerators optimized for peak per-operator speed, this design prioritizes asynchronous co-executionbetween the processing system (PS, the dual-core Cortex-A9) and the programmable logic (PL): The PL performs tiled matrix multiplication, while the PS executes preprocessing, orchestration, and I/O data concurrently, increasing effective end-to-end throughput regardless of the relative isolated performance of CPU and FPGA. The proposed module includes high-level-synthesis (HLS)-based matrix multiplication, activation functions, and Advanced eXtensible Interface (AXI)-Stream Direct Memory Access (DMA) interfaces, wrapped as custom PyTorch kernels under the PetaLinux operating system. The results obtained on the PYNQ-Z2 board show that, once the DMA transfer time is included in the measurement, the FPGA path does not surpass Cortex-A9 in isolated per-operator latencies across the evaluated range; the benefit lies instead in delegating the matrix compute to the fabric at low incremental power while the host CPU cores stay available for concurrent tasks. A concurrent workload sweep across matrix sizes from 8×8 to 256×256 confirms that the co-execution mode sustains 98–99% of available PS compute throughput compared with a constant ≈50% in single-core blocking mode; the difference is statistically significant for all evaluated sizes (see Mann–Whitney U: U=25, p=3.97×10−3, perfect discrimination, n=5). A fair dual-core CPU-only baseline attains comparable PS availability, so this figure reflects the dual-core scheduling that co-execution enables rather than a per-operator advantage of the fabric; the accelerator’s distinct role is to perform the matrix arithmetic off the general-purpose cores at low incremental power. The design occupies only 8% of available look-up tables (LUTs) and 5% of digital signal processing (DSP) blocks, maintains 1.69 W power with a junction temperature of 44.5 °C, and achieves 96.10% MNIST accuracy under fixed-point arithmetic.
Omar Hernandez-Yañez, A. Juárez-Lora, J. Y. Montiel-Pérez et al.· Electronics· 0 citations
Heterogeneous DRAM-based processing-in-memory (PIM)-GPU systems promise significant efficiency gains for decode-phase large language model (LLM) inference, particularly in long-output generation, yet current design practices overlook critical factors that determine real-world performance. Through systematic evaluation of diverse architectures and workloads (OPT-7B/70B, Mamba2-2.7B/70B), we reveal three fundamental design principles: (i) static power consumption (DRAM leakage, refresh, and GPU idle power) can dominate the efficiency calculus, causing dynamic-only models to overestimate tokens/s/W by up to 3.85X for realistic deployments (Mamba2-2.7B, batch size 1, 128 input tokens, and 2,048 output tokens); (ii) decoding performance is monotonically non-decreasing with channel count across all evaluated models and workloads, generally plateauing at high channel counts for low-batch workloads; under a fixed-capacity sweep, all models instead share a common near-optimal hierarchy configuration, with substantially larger misconfiguration penalties for attention-based models; (iii) workload mapping strategies provide bounded improvements (up to 14.0%/17.4% kernel-level latency/energy reduction, up to 5.6% end-to-end gain) and are not primary bottlenecks. Significant efficiency gains require system-wide co-optimization. These principles provide design-space guidance for architects designing the next generation of memory-accelerated LLM systems.
Corey Lammie, Hadjer Benmeziane, W. Simon et al.· 0 citations
Non-volatile memory (NVM) technologies, particularly Multi-Level Cell (MLC) NVMs, offer significant potential for increasing memory density. MLC NVMs provide a tradeoff between write latency and retention time, where faster writes/stores result in lower retention and slower writes yield higher retention. However, limited work has been done to validate and prototype NVM-based systems in hardware, leveraging this tradeoff at the system level. In this paper, we present a novel memory controller architecture and a RISC-V instruction set extension to optimize MLC NVM write operations by balancing speed and retention time. Our custom NVM controller, built around a finite state machine with an AXI memory-mapped interface, efficiently manages read/write operations with enhanced burst transfers, minimizing latency. Additionally, we introduce a fast-store instruction in RISC-V to increasing write performance while addressing retention limitations. Further, we design a dedicated AXI slave peripheral that supports bit-significance-aware writes: critical bits (e.g., MSBs) are written using slower, high-retention writes, while non-critical bits (e.g., LSBs) use faster, low-retention writes to help enhance performance without compromising data reliability. These enhancements are implemented in hardware on an FPGA platform. Experimental results show that our controller reduces hardware overhead by 30% compared to conventional designs, and the fast-store instruction improves performance by over 7% for streaming workloads with less than 0.08% hardware overhead. The bit-wise AXI peripheral has a LUT utilization staying below 3.5% even for 64x64 matrices, and under 1% for 32x32 sizes, making it viable for integration into larger SoCs.
Mina Ibrahim, M. Shokry, Lokesh Siddhu et al.· 0 citations
Edge intelligence applications demand high-throughput and energy-efficient hardware accelerators under strict power, latency, and resource constraints in real-time environments. Conventional compute-centric architectures rely heavily on sequential multiply-accumulate (MAC) operations and frequent off-chip memory access, resulting in high energy consumption, increased latency, and bandwidth bottlenecks. These limitations become more pronounced as neural network models scale in size and complexity. While Ternary Content-Addressable Memory (TCAM) offers an alternative through parallel associative search and constant-time pattern matching, it suffers from excessive power consumption and limited adaptability due to continuous match-line activation. This work proposes a hybrid SRAM-TCAM memory-centric deep neural network (DNN) architecture that integrates three tightly coupled subsystems. First, a two-layer autoencoder with ReLU activations compresses 128-bit input feature vectors to 32-bit latent codes, achieving a compression ratio η=4×\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\eta = 4\times $$\end{document} and a 75%\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$75\%$$\end{document} BRAM saving. Second an on-chip dual-port BRAM data-locality buffer exploits the compressed representation to eliminate inter-layer off-chip DRAM accesses in the critical inference path. Third, a 256×32\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$256 \times 32$$\end{document}-bit Ternary Content-Addressable Memory array provides O(1) parallel associative inference. A software-only Genetic Algorithm (GA) with Roulette Wheel Selection (RWS) optimizes TCAM configuration offline prior to FPGA deployment; the converged 8,480-bit chromosome is loaded once at startup and remain static during inference, adding zero dynamic power overhead. The proposed architecture, implemented on a Xilinx Artix-7 FPGA, achieves a 42.3%\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$42.3\%$$\end{document} reduction in power compared to a conventional MAC-based baseline (120.5 mW vs. 208.7 mW), an end-to-end throughput of 108.47 Mops reflecting steady-state pipelined operation at 108.47 MHz (2.42×\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$2.42\times $$\end{document} speedup), and an inference accuracy of 95.3%\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$95.3\%$$\end{document} – a 1.5%\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$1.5\%$$\end{document} degradation attributable to quantization, evaluated on the benchmark dataset. Power figures are obtained from the Vivado Power Estimator tool (post-implementation) at nominal supply voltage of 1 V. These results demonstrate an efficient and scalable solution for next-generation edge AI inference systems.
Vandana Thakur, V. More, Abhishek Bhatt· Journal of King Saud Univers...· 0 citations
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