Sep 2026· IEEE Transactions on Circuits and Systems Part 1: Regular Papers· Vol 73, pp. 6249-6262· 0 citations· 34 references
Abstract
ReRAM-based in-memory computing (IMC) architectures enable efficient neural-network inference on edge devices, due to their high density and non-volatility. However, ReRAM is prone to the stuck-at faults (SAFs) which would distort weight mappings and reduce model accuracy substantially. To tackle this problem, a high-efficiency fault-resilient (HE-FR) framework is introduced in the paper, which couples layered-precision quantization based on the generalized gaussian distribution cumulative distribution function (GGD-CDF), preserving weight distributions with the minimal information loss. Further, a fault-aware weight re-decomposition method is proposed. Specifically, a Q-agent-based method is proposed for sparse SAFs, which employs offline reinforcement learning to construct a globally optimized hash table with reduced compilation complexity, while incorporating both weight matching and cell-state stability into the reward function to suppress electro-stress. For dense SAFs, we exploit a greedy search over the remaining cells to provide rapid and accurate mappings. Experimental results show that GGD-CDF quantization improves accuracy by 2.18% over Float32. Under fabrication faults, HE-FR surpasses a fault-free method by 12.97% and accelerates compilation by $197\times $ with only 0.024% picojoule-level energy overhead. In electro-stress evaluations, HE-FR reduces performance degradation by 46.27%. It demonstrates that the proposed framework has advantages in robustness, efficiency, and reliability.
Resistive random-access memory (ReRAM)-based in-memory computing (IMC) systems provide high energy efficiency and storage density for deep neural network (DNN) acceleration, but stuck-at faults (SAFs) substantially degrade reliability. Weight remapping (WR) can mitigate SAFs; however, existing approaches either ignore dataflow consistency or require additional hardware to restore it. We propose FREEMAP, an overhead-free WR algorithm that preserves dataflow consistency without runtime operations or hardware modifications. FREEMAP combines layer-wise filter reordering (LFR), which globally reorders filters across a layer for fault resilience, with row group remapping (RGR), which realigns the next layer's weight rows to the reordered outputs. Across diverse models and datasets, FREEMAP eliminates the hardware overhead of conventional WR, reducing area and energy to 0.02×-0.06× and 0.04×-0.14×, respectively. Compared with state-of-the-art dataflow-aware WR, it further reduces area and energy to 0.45×-0.47× and 0.52×-0.63× while maintaining comparable accuracy.
Hyeonsu Bang, Jong Hwan Ko· Proceedings of the ACM/IEEE...· 0 citations
The massive data-movement overhead in traditional architectures has led to the adoption of In-Memory Computing (IMC) for energy-efficient Deep Neural Network (DNN) processing. By leveraging emerging devices like Spin-Orbit Torque Magnetic Tunnel Junctions (SOT-MTJs), IMC bypasses the"memory wall"and reduces leakage power inherent in traditional CMOS. However, this shift introduces dual hardware threats: manufacturing Process Variation (PV) degrades reliability and increases vulnerability to fault injection, while power Side-Channel Attacks (SCAs) compromise security. Existing defenses address these threats in isolation. This work presents a posttraining framework that simultaneously hardens analog IMC accelerators against both threats without retraining the model. Implemented in the IMAC-Sim simulator, our approach uses the proposed Variation Impact Score (VIS) to guide the mapping of Fault Observation Windows (FOWs) and introduces the Leakage Per Inference (LPI) metric to quantify input-dependent power variability under stochastic injection and the resulting reduction in effective signal-to-noise ratio. Experiments show that PV-induced faults can degrade accuracy by over 50%, while our method restores near-baseline accuracy and mitigates the threat of correlation-based power analysis attacks.
Muhtasim Alam Chowdhury, Ramtin Zand, Soheil Salehi· 0 citations
Processing in memory (PIM) offers a compelling pathway to overcome the data movement bottleneck in modern AI and data-centric systems. This work introduces MITRA, a reconfigurable magnetic tunnel junction (MTJ)-based in-memory architecture that leverages stochastic computing (SC) to implement a broad class of transcendental and nonlinear functions directly within memory. By combining stochastic bit-stream processing with compact finite-state-machines (FSMs) embedded in MTJ-FinFET logic-in-memory structures, the proposed design achieves low-latency and power-efficient computation without external datapaths, unlike the binary counterparts. Circuit-level simulations in 14-nm FinFET technology verify correct state transitions, stable stochastic outputs, and predictable power profiles. Extensive evaluations demonstrate high accuracy even with short bit-streams. We further integrate the design into a neural-network classifier and develop an FSM-aware training strategy that compensates for approximation errors, achieving up to 96.9% classification accuracy on the UCI Optical Digit benchmark. Overall, MITRA provides a compact, reconfigurable platform for nonlinear processing in next-generation edge AI systems.
Farzad Razi, M. Moghadam, M. Najafi et al.· Proceedings of the ACM/IEEE...· 0 citations
Quantized Neural Networks~(QNN) with low-bitwidth data have proven promising in efficient storage and computation on edge devices. To mitigate accuracy degradation while maximizing speedup, layer-wise mixed-precision quantization~(MPQ) becomes a popular solution. However, existing algorithms for exploring MPQ schemes are limited in flexibility and efficiency. Comprehending the complex impacts of different MPQ schemes on post-training quantization and quantization-aware training results is a challenge for conventional methods. Furthermore, an end-to-end framework for the optimization and deployment of MPQ models is missing in existing work. To address these challenges, we propose the MiCo framework, a holistic MPQ exploration and deployment framework for edge AI applications. The framework adopts a novel optimization algorithm to search for accuracy-optimal quantization configurations under strict latency constraints. We further extended the framework to MiCoPro, which introduces a robust Hardware-Aware Proxy (HAP) model to enhance prediction accuracy and hardware versatility. By leveraging target-specific latency modeling, MiCoPro enables rapid exploration and direct deployment from PyTorch models to bare-metal C code. We demonstrate the versatility of our framework on both the BitFusion accelerator and SIMD-extended RISC-V processors, achieving up to 40\% of latency reduction with less than 3\% of accuracy drop.
While Large Language Models (LLMs) have gained remarkable success, they are consistently at risk of being stolen when deployed on untrusted edge devices. As a solution, TEE-based secure inference has been proposed to protect valuable model property. However, we identify a statistical vulnerability in existing protection methods, and furtherly compromise their security guarantees by proposed Model Stealing Attack with Prior. To eliminate this vulnerability, LoRO is presented in this paper, which leverages dense mask to completely obfuscate parameters. LoRO includes two innovations: (1) Low Rank Mask, which uses low-rank factors to generate dense masks efficiently. The computing complexity in TEE is hence reduced by an exponential amount to achieve inference speed up, while providing robust model confidentiality. (2) Factors Multiplexing, which reuses several cornerstone factors to generate masks for all layers. Compared to one-mask-per-layer, the secure memory requirement is reduced from GB-level to tens of MB, hence avoiding the hundred-fold latency introduced by secure memory paging. Experimental results indicate that LoRO achieve a 0 . 94 × Model Stealing (MS) accuracy, while SOTA methods presents 3 . 37 × at least. The averaged inference latency of LoRO is only 1 . 49 × , compared to the 112 × of TEE-shielded inference. Moreover, LoRO results no accuracy loss, and requires no re-training and structure modification. LoRO can solve the concerns regarding model thefts on edge devices in an efficient and secure manner, facilitating the wide edge application of LLMs.
Gaojian Xiong, Yu Sun, Jianhua Liu et al.· Advances in Neural Informati...· 5 citations
Time-Sensitive Networking (TSN) is critical to deterministic communication in safety-critical domains, with formal verification such as Network Calculus (NC) serving as the cornerstone for schedulability guarantees. However, during automated configuration-space exploration, repeated schedulability analysis consumes over 90% of the total configuration time, becoming the primary bottleneck for large-scale TSN configurations. To address this challenge, we propose DeepNC, a novel pre-verification surrogate module that pioneers the structural fusion of NC principles into a Graph Neural Network (GNN) for TSN configuration-space exploration. Rather than replacing formal verification, DeepNC acts as a high-speed pre-verification filter, reserving computationally expensive formal verification only for promising candidates. Extensive evaluations demonstrate that DeepNC significantly improves worst-case delay prediction accuracy over state-of-the-art learning-based methods, increasing the average $R^2$ by 55.8% and reducing the average MAPE by 65.3%. More importantly, its high-fidelity regression substantially reduces the number of formal verification calls during configuration-space exploration by 93.25%, while accelerating NC-based verification by more than two orders of magnitude.
Jiayi Zhu, Jing Lin, Zelong Tian et al.· 0 citations
Related blog posts
MIT News · Artificial Intelligence· news.mit.eduSep 2, 2026
What if pathology foundation models could do more with less? GigaPath-Flash and GigaTIME-Flash cut computational demands while maintaining strong performance, opening the door to larger studies and broader exploration. The post GigaPath-Flash and GigaTIME-Flash: Toward population-scale discovery with efficient pathology foundation models appeared first on Microsoft Research.
MIT News · Artificial Intelligence· news.mit.eduAug 31, 2026
With millions of users across the world, Julia has been used to conduct cutting-edge research and to design new drugs, jet engines, heat pumps, and more.
MIT News · Artificial Intelligence· news.mit.eduAug 27, 2026
A new machine-learning framework aims to improve the success rate of computational protein design while moving away from results that reproduce sequences found in nature.
