MITRA: Reconfigurable, Low-Latency, and Power-Efficient In-Memory Stochastic Architecture for Transcendental Functions

Abstract

Processing in memory (PIM) offers a compelling pathway to overcome the data movement bottleneck in modern AI and data-centric systems. This work introduces MITRA, a reconfigurable magnetic tunnel junction (MTJ)-based in-memory architecture that leverages stochastic computing (SC) to implement a broad class of transcendental and nonlinear functions directly within memory. By combining stochastic bit-stream processing with compact finite-state-machines (FSMs) embedded in MTJ-FinFET logic-in-memory structures, the proposed design achieves low-latency and power-efficient computation without external datapaths, unlike the binary counterparts. Circuit-level simulations in 14-nm FinFET technology verify correct state transitions, stable stochastic outputs, and predictable power profiles. Extensive evaluations demonstrate high accuracy even with short bit-streams. We further integrate the design into a neural-network classifier and develop an FSM-aware training strategy that compensates for approximation errors, achieving up to 96.9% classification accuracy on the UCI Optical Digit benchmark. Overall, MITRA provides a compact, reconfigurable platform for nonlinear processing in next-generation edge AI systems.