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Author

M. Najafi

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Preprint Aug 2026

A Low-Latency ASIC Architecture for Real-Time Line Segment Detection

The proposed design is based on the step-length algorithm and incorporates five ASIC-specific features: register-based line buffering with data reuse, multiplierless MCM-based filtering, 8-class angle quantization, a CAM-like associative memory for single-cycle matching, and an optimized duplicate removal mechanism.

Amir Hossein Jalilvand, P. Panahi, M. Najafi · 2 citations
Review Aug 2026

Hardware-Enabled Fuzzy Inference: Architectures, Platforms, and Emerging Trends

This survey presents the first comprehensive, platform-centric review of hardware fuzzy systems, systematically organizing the literature into three principal categories: FPGA-based implementations, ASIC and custom VLSI realizations, and embedded, IoT, and TinyML platforms.

Amir Hossein Jalilvand, P. Panahi, M. Najafi · 0 citations
#artificial intelligence Preprint Sep 2026

Hardware-Aware Learned Representation Compression for Distributed In-Sensor Vision

OASIS, a distributed in-sensor vision framework that uses a lightweight encoder to generate compact, task-relevant representations before off-chip transmission, is presented, demonstrating a practical hardware-algorithm co-design path for communication-efficient in-sensor vision.

Cheng-Wei Zhou, Abu Masum, Xu-Ming Chen et al. · 0 citations
Book Open access Aug 2026

MITRA: Reconfigurable, Low-Latency, and Power-Efficient In-Memory Stochastic Architecture for Transcendental Functions

This work introduces MITRA, a reconfigurable magnetic tunnel junction-based in-memory architecture that leverages stochastic computing (SC) to implement a broad class of transcendental and nonlinear functions directly within memory.

Farzad Razi, M. Moghadam, M. Najafi et al. · 0 citations

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