Design Space Exploration of In-Memory Computing Implementations for Discrete Fourier Transform
TL;DR
A comprehensive hardware-aware design framework for systematically mapping algorithmic workloads onto IMC architectures, using the discrete Fourier transform (DFT) as a case study and a novel mapping scheme that reduces energy consumption per computation by 53% compared with conventional mapping techniques is introduced.
Abstract
Although memristor-based in-memory computing (IMC) has been widely investigated for brain-inspired neuromorphic workloads, systematic evaluations of its energy, latency, and signal-to-noise ratio (SNR) trade-offs across diverse system parameters remain scarce for classical digital signal processing (DSP). To address this gap, this paper introduces a comprehensive hardware-aware design framework for systematically mapping algorithmic workloads onto IMC architectures, using the discrete Fourier transform (DFT) as a case study. Tailored to the stringent performance requirements of a DFT accelerator for 5G orthogonal frequency-division multiplexing (OFDM) systems, we propose a novel mapping scheme that reduces energy consumption per computation by 53% compared with conventional mapping techniques. Additionally, we present a comparative study of resistive random-access memory (RRAM) and ferroelectric tunnel junction (FTJ) technologies with identical numbers of programmable states but distinct conductance ranges, demonstrating the importance of device-informed architectural co-design. By bridging the gap between emerging IMC architectures and rigid DSP constraints, this work provides a pathway toward energy-efficient edge accelerators for future wireless communication systems.