SoK: From Silicon to Netlist and Beyond Two

SoK: From Silicon to Netlist and Beyond

This work presents the first large-scale Systematization of Knowledge of Knowledge of the HRE workflow, analyzing 187 peer-reviewed publications and derives stakeholder-specific recommendations for academia, industry, and government to transition HRE from isolated research silos toward a collaborative discipline capabl...

Hardware Design and Security in the Era of Chiplets and LLMs

A unified analysis of attacks on chiplet systems, the integration of Large Language Models into Electronic Design Automation (EDA) flows, and how LLM systems can advance hardware security efforts for modern systems, including chiplets is provided.

Firmware Reverse Engineering: A Comprehensive Review and Directions

This review synthesises 118 works published from 2014 to 2026 covering the full firmware reverse engineering pipeline and identifies ten structural gaps, including the absence of unified evaluation benchmarks, fragmented peripheral modelling, the scalability–fidelity trade-off in re-hosting, and insufficient grounding...

POSTER: VibeNIC: Toward LLM-driven Agile Development of FPGA SmartNICs

VibeNIC is a SmartNIC framework co-designed at every layer for an LLM developer, and a case study on a stateful HBM-augmented UDP datapath delivers a working end-to-end design in hours.

Advanced Security through Hardware Capabilities: A Comprehensive Survey on CHERI Technology

A detailed survey of CHERI technology is provided, covering its historical evolution, key concepts, and current hardware and software implementations, and the ongoing challenges of its adoption in industry, the research efforts driving its growth as well as speculating and discussing future research directions.

An Efficient Gate-Level Logic and Structural Analysis Framework for Hardware Trojan Detection