Resource-Aware Co-Design of Spiking Neural Networks for Intelligent Structural Health Monitoring on Edge FPGAs
TL;DR
A Hardware–Software Co-Design Framework that enables deployment of a Spiking ResNet-18 for automated crack detection on a Xilinx KV260 edge FPGA, and develops Channel Folding, a novel High-Level Synthesis (HLS) architecture reducing intermediate buffers by 4 × .
Abstract
: Deploying deep Spiking Neural Networks (SNNs) on resource-constrained Field-Programmable Gate Arrays (FPGAs) for Structural Health Monitoring (SHM) is hindered by the persistent storage of neuronal membrane potentials across timesteps, creating a substantial on-chip memory requirement that standard Convolutional Neural Network (CNN) acceleration techniques do not directly address. We propose a Hardware–Software Co-Design Framework that enables deployment of a Spiking ResNet-18 for automated crack detection on a Xilinx KV260 edge FPGA. The framework formalizes the Membrane Memory Floor (MMF) as a lower bound on on-chip memory for the target deployment architecture, introduces Proportional Channel Scaling (PCS) for systematic topology reduction, applies Memory Type Selection (MTS) to optimally bind state arrays to heterogeneous BlockRAM (BRAM) and UltraRAM (URAM) resources, and develops Channel Folding, a novel High-Level Synthesis (HLS) architecture reducing intermediate buffers by 4 × . Evaluated on the SDNET2018 dataset, the framework achieves 85.89 ± 0.40% accuracy while reducing BRAM utilization by 71.7% and DSP usage by 87%, fitting a deep residual SNN onto a platform where the baseline requires 300% of available memory. Ablation analysis confirms that only the combined application of all techniques satisfies the strict resource constraints. Board-level measurements on the deployed KV260 platform report a dynamic power consumption of only 0.321 W during active SNN inference, demonstrating the suitability of the proposed framework for low-power autonomous SHM at the network edge.