ANP-Flow: A System-Level Simulation and Performance Prediction Toolchain for Asynchronous Neuromorphic Hardware Enabling Co-Exploration

Abstract

Energy-efficient neuromorphic hardware with ultralow power consumption is increasingly promising for edge–artificial intelligence (AI) applications. Most digital neuromorphic hardware is designed with asynchronous circuits as they naturally match the sparsity and event-driven features of neuromorphic computing. However, designing asynchronous neuromorphic hardware faces challenges, including a lack of system-level hardware simulators and performance prediction methods, making it difficult for designers to explore the nonnumeric architecture design space of asynchronous neuromorphic hardware and find an optimal architecture that meets the demands for various edge computing scenarios. In this article, we put forward asynchronous neural processor (ANP)-Flow, a toolchain for asynchronous neuromorphic hardware including system-level simulation, performance prediction, and algorithm–hardware co-exploration. The key innovations include: 1) a fully asynchronous, highly concurrent system-level simulator is developed for the first time, enabling fast simulations for asynchronous neuromorphic hardware; 2) a novel graph neural network (GNN)-based hardware latency prediction model and a residual network (ResNet)-based power consumption prediction model are presented for asynchronous neuromorphic hardware. Experimental results show that they, respectively, achieve over 0.9 of average $R_{2}$ score and less than 2% of mean average percentage error (MAPE) rate on datasets with various network scales, traffic patterns, and process nodes; and 3) an algorithm–hardware co-exploration framework is proposed, improving energy-delay product of asynchronous neuromorphic hardware design by 1.8 times compared with the state-of-the-art (SOTA) work. To the best of our knowledge, ANP-Flow is the first end-to-end asynchronous neuromorphic toolchain with an integrated framework from circuit to algorithm, enabling joint algorithm–hardware design space co-exploration.