NanoLogicController: A Minimal Open-Source ASIP for Accelerated Gate-Level Netlist Emulation

Abstract

Following Moore's Law, the ever-increasing complexity, i.e., the number of logic gates, of digital systems poses significant challenges for verification at the netlist (i.e., logic gate) level. On the one hand, the inherent bit-level parallelism exposed by netlists cannot be efficiently exploited to accelerate simulations on traditional multicore general-purpose processors. On the other hand, emulation systems based on multiple FPGA devices suffer from netlist partitioning overhead as well as excessively long EDA runtime for synthesis and place-and-route. In order to solve these issues, a manycore system based on specialized logic emulation processor cores can be used to exploit the inherent netlist parallelism, while reducing preparation time and providing improved debugging facilities via utilizing a software compiler. This work focuses on the logic emulation processor core, proposing an open-source application-specific instruction-set processor, called NanoLogicController, for gatelevel circuit emulation. The NanoLogicController architecture features a minimal control path and a lookup-table-based data path design, specialized for the evaluation of logic gate functions, which are converted into program code via a Verilog netlist parser and a custom code generation tool. Due to stack-based data organization inside the data path, a very compact 4-bit-wide instruction-set and instruction encoding can improve program code density and reduce instruction memory requirements. In a post-synthesis evaluation using a 22 nm FDSOI CMOS technology, the minimal core architecture achieves a maximum clock frequency of 6 GHz and requires only $\mathbf{3 8 2 7} \boldsymbol{\mu m}^{\mathbf{2}}$ of silicon area including memories. This paves the way for integrating an opensource high-performance, massively parallel manycore netlist emulator with up to approx. 250 cores/ $\mathbf{m m}^{\mathbf{2}}$ in future work.