FPGA Implementation of a Low-Power VLSI Architecture for Medical Image Scaling

Abstract

This paper presents an FPGA (Field-Programmable Gate Array) implementation of a low-power VLSI (Very Large-Scale Integration) architecture for medical image scaling in portable diagnostic systems. The proposed architecture employs bilinear interpolation optimized through FSM (Finite-State-Machine)-based control, a clock-enable technique, and selective block activation to reduce switching activity and dynamic power consumption while preserving image quality. The architecture is described in Verilog HDL, synthesized using Vivado 2024.1, and implemented on the Xilinx Zynq-7000-based ZedBoard platform. A controlled post-implementation power analysis on the same FPGA platform demonstrates a reduction in estimated total on-chip power from 3.739 W for the unoptimized baseline architecture to 1.053 W for the optimized architecture, corresponding to an approximately 71.8% reduction. The system supports multiple operational modes, including original image display, grayscale conversion, Sobel X filtering, and Sobel Y filtering, providing enhanced diagnostic flexibility. Quantitative assessment of the exemplary X-ray Image 1 yielded PSNR (Peak Signal-to-Noise Ratio) of 42.97 dB and SSIM (Structural Similarity Index) of 0.9557, demonstrating satisfactory image-quality preservation after scaling. The proposed architecture demonstrates the feasibility of low-power FPGA-based medical image scaling for portable diagnostic and telemedicine imaging systems, offering an effective balance between energy efficiency and image fidelity.