2026· Proceedings of the 23rd International Conference on Security and Cryptography· pp. 459-464· 0 citations· 20 references
TL;DR
This work presents an optimized software implementation providing 1 st -order side-channel protection, as well as the first efficiency-oriented 2 nd -order implementation, surpassing previous solutions in performance.
Abstract
: The K ECCAK core is a fundamental cryptographic primitive widely used in post-quantum cryptography to ensure security against emerging quantum-computing attacks. Secure software implementations rely on masking schemes to mitigate side-channel leakage, but these protections introduce significant overhead, which is particularly impactful on resource-constrained microcontrollers and further exacerbated by micro-architectural leakages. To date, publicly available masked K ECCAK implementations do not achieve both efficiency and robustness against such leakages. This work presents an optimized software implementation providing 1 st -order side-channel protection, as well as the first efficiency-oriented 2 nd -order implementation, surpassing previous solutions in performance. Both implementations target the ARM Cortex-M4 microcontroller and satisfy constraints to prevent micro-architectural leakages. A public repository provides the source code and a labeled dataset of 500K+500K traces, enabling reproducibility. Benchmarks show a 44.1% improvement over previously reported first-order implementations.
Cryptographic hardware implementations often leak secret information through side channels. This can allow attackers to learn secret data, such as a cryptographic key, without any vulnerability in the cryptographic algorithm itself. A popular countermeasure to such attacks is masking, which ensures that processed data is independent of the secrets by splitting them into multiple independent shares, often at the cost of significant overhead in terms of required area, latency, and randomness. The composable PINI notion in the glitch-extended probing model ensures some degree of security against such side-channel analysis attacks, and guarantees that the circuit may be arbitrarily composed with other PINI circuits while maintaining the same security level. This allows for the secure implementation of arbitrary circuits using trivial composition, replacing elementary gates with “gadgets” realizing the same functionality in a PINI-secure manner. Up to now, PINI gadgets at arbitrary security order are limited to quadratic functions, i.e., 2-input gates, with the best known as HPC3.X realizing a 2-input multiplier in one clock cycle.In this work, we present HPCC, the first low-latency 3-input multiplication gadget for arbitrary fields that maintains a constant latency of one cycle, independent of the number of shares. HPCC additionally allows for the computation of any number of multiplications in a single cycle with relatively little overhead when two of the three operands are identical. When instantiated with two shares and for F2, HPCC halves the previous record for lowest number of fresh masks required at comparable area cost. With more shares, HPCC is the only single-cycle gadget realizing 3- input multiplications in arbitrary fields. We leverage HPCC to implement the first composable AES S-Box with two cycles of latency with an arbitrary number of shares. This S-Box design significantly outperforms the previous record in terms of area and randomness when instantiated with three shares and stands as the only two-cycle solution for more shares.
Frederik Reiter, Amir Moradi· IACR Transactions on Cryptog...· 0 citations
Securing memory in resource-constrained embedded systems remains a critical challenge due to the susceptibility of statically stored cryptographic keys to physical and sidechannel attacks. This paper presents a lightweight memory obfuscation architecture based on Physical Unclonable Functions (PUFs), utilizing the intrinsic manufacturing variations of Arbiter PUFs (APUFs) to generate device-specific encryption keys dynamically at runtime, thereby eliminating the need for persistent key storage. The proposed system employs a hardware-rooted XOR-based encryption scheme in which memory addresses are transformed into challenges to produce unique, non-stored keystreams for memory protection. The architecture is implemented on an FPGA platform using a MicroBlaze-based system, integrating a custom XOR encryption engine and a finite state machine (FSM) for secure access control and device authentication. Experimental results demonstrate strong statistical security properties, with ciphertext achieving near-ideal entropy (7.9987 bits/byte), negligible correlation with plaintext, and a uniform distribution under chi-square testing. Furthermore, the design exhibits low hardware overhead, utilizing only 3.15% of LUT resources and consuming 0.235 W, highlighting its suitability for IoT and resource-constrained applications. These results confirm that PUF-based dynamic key generation combined with lightweight XOR encryption provides an effective and efficient hardware-rooted solution for memory protection.
Qabas Alkaissi, Selen Qarajeh, Jana Falah et al.· IEEE Jordan Conference on Ap...· 0 citations
FPGAs are increasingly deployed in security-critical applications, where both design confidentiality and operational reliability are paramount. To protect IP, safeguard cryptographic secrets, and prevent unauthorized modifications or hardware Trojan insertion, modern hardware platforms employ bitstream encryption. Built-in reliability features, often required by safety regulations, detect and correct singleevent upsets, i.e., bit flips, caused by ionizing radiation. However, these reliability mechanisms can inadvertently compromise bitstream confidentiality.In this work, we present Leakback CRC, the first optical side-channel attack exploiting the Readback CRC functionality in AMD 7-Series FPGAs to recover plaintext configuration data of encrypted bitstreams. Our attack utilizes contactless optical probing to monitor periodic configuration memory accesses by the Readback CRC circuitry. This novel attack results in full netlist reconstruction, even though dynamically changing runtime data cannot be retrieved, as it is not verified by the Readback CRC. After presenting the attack in a case study on an AMD 7-Series FPGA, we discuss its limitations and potential countermeasures, as well as its applicability to other FPGA platforms. Our findings highlight a critical interplay between reliability mechanisms operating on plaintext configuration data and side-channel leakage, underscoring the need to broaden the threat model underlying built-in reliability features in reconfigurable hardware.
Antonio Saavedra, Lars Renkes, F. Hahn et al.· IACR Transactions on Cryptog...· 0 citations
The threat of practical quantum attacks has catapulted viable alternatives like Post-Quantum Cryptography (PQC) into prominence. The adoption and integration of standardized PQC primitives across the entire digital stack are promoted by various standardization bodies, governments, and major corporate houses. A serious challenge in quantum migration is to ensure that there is no hidden backdoor in the PQC implementations of a hybrid cryptosystem (support for both pre-quantum and post-quantum algorithms), which are often procured from a third-party vendor. In this manuscript, we investigate the possibility of a Kleptographic backdoor on the NIST-recommended key-encapsulation mechanism CRYSTALS-Kyber. The modified Kyber Key-Generation() algorithm achieves indistinguishable decryption failure probability compared to the original CRYSTALS-Kyber. The Kleptographic module is also implemented in FPGA, embedded inside the CRYSTALS-Kyber accelerator with a very low area overhead (283 LUTs or 2% of total area), and thus can easily pass performance and functionality tests.
Suraj Mandal, Prasanna Ravi, M. Dhilipkumar et al.· ACM Transactions on Embedded...· 0 citations
Transport Layer Cryptography Protocol (TLCP) is a secure communication protocol developed in China, featuring a dual-certificate architecture and incorporating ShangMi cryptographic algorithms. It has been widely deployed in security-critical domains such as finance, government, and energy. Despite its practical significance, TLCP did not undergo comprehensive formal analysis during its standardization process, leaving potential design-level vulnerabilities insufficiently explored. Moreover, the advent of quantum computing poses fundamental challenges to the classical cryptographic primitives employed by TLCP, motivating the need for both systematic security evaluation and post-quantum enhancements. To address these gaps, we first construct the comprehensive formal model of TLCP, covering certificate-based and identity-based cipher suites as well as its distinctive dual-certificate mechanism, under a realistic threat model and security assumptions that capture both classical and quantum adversaries. Based on this model, we conduct an automated security analysis using ProVerif, identifying nine potential attack vectors and deriving five concrete mitigation recommendations. Finally, motivated by the analysis results and the limitations of incremental fixes against quantum threats, we propose KEMTLCP, a post-quantum secure variant of TLCP that leverages key encapsulation mechanisms (KEMs) for both key exchange and authentication while preserving TLCP’s architectural principles through a novel explicit authentication mechanism. We further provide a security proof for the core authentication mechanism, show that KEMTLCP effectively mitigates the majority of identified vulnerabilities through formal analysis, and evaluate its practical performance.
Hongbo Liu, Jingnan He, Jia-ao Ge et al.· Cybersecurity· 0 citations
Post-quantum cryptography has become pivotal for ensuring communication security in the quantum era. NTRU-based signature schemes have gained attention due to their computational efficiency and compact public keys and signatures, which reduce communication overheads. However, the algebraic structure of NTRU lattices introduces vulnerabilities in physicalattack scenarios, where partial secret key leakage can severely un-dermine system security. In this paper, we propose the Dimension-and-Sample Reduced NTRU Attack (DSRNA). The core principle of DSRNA is to apply a dimension-reduction strategy that transforms the NTRU instance into a lower-dimensional NTRU instance with fewer samples, which is efficiently solvable via lattice basis reduction. Furthermore, we design a unified hint-embedding technique that jointly exploits side information from both secret keys f and g, thereby improving both attack efficiency and success rates. We evaluate the residual security of Falcon and its variants Mitaka and Hawk, under perfect, modular and approximate leakage models. Experimental results demonstrate security degradation. Compared to the method of May et al. at Asiacrypt 2023, DSRNA achieves speedups of 5.8× for Falcon-512 with 400 leaked coefficients and over $29.4 \times$ for Falcon-1024 with 905 coefficients. This study reveals the potential vulnerability of NTRU-based signature schemes to partial secret key leakage.