Active Disturbance Rejection Control for Robust DC Bus Regulation in Standalone Multistage Inverters

Abstract

This paper addresses DC bus voltage regulation in standalone multistage inverters, where the DC‐DC stage must maintain a stable bus voltage despite input voltage fluctuations, unpredictable load changes, and model uncertainties. An Active Disturbance Rejection Control (ADRC) strategy is proposed for the push‐pull converter stage, in which all disturbances are lumped into a single generalized disturbance estimated in real time by an extended state observer (ESO) using only a single voltage sensor. The DC‐AC stage is treated as an unknown load and controlled independently. Stability and convergence of the closed‐loop system are formally established via Lyapunov analysis, with the design reduced to two bandwidth parameters. The structural equivalence between ADRC and a PID controller with a second‐order low‐pass filter is derived, which reveals that ADRC preserves low‐frequency regulation while providing inherent high‐frequency noise attenuation. Comparative simulations confirm this advantage under measurement noise. The proposed strategy is experimentally validated on a 1.6 kW, 24 V/230‐Vrms prototype under start‐up transients, variable references, resistive, constant current, and nonlinear loads. Experimental results further confirm robustness to control‐gain mismatch caused by battery voltage variation, transparently compensated by the observer without requiring precise plant knowledge.