Post-Quantum Safe and Side Channel Attack Resilient ARM Cortex M4 Satellite Uplink

Abstract

As satellite communication infrastructure shifts toward a post-quantum-secure paradigm, the integration of NIST Round 4 candidates such as Hamming Quasi-Cyclic (HQC) codebased cryptography enables secure and efficient satellite uplink communication under stringent power and latency constraints. However, the migration of HQC to resource-constrained devices, such as the STM32, introduces physical-level vulnerabilities to side-channel attacks (SCA). This paper proposes a side-channelresilient implementation of the HQC-128 polynomial multiplication for ARM Cortex-M4-based satellite uplink systems, specifically hardened against Simple Power Analysis (SPA) attacks. To mitigate secret key leakage, we implement a hybrid countermeasure strategy combining stochastic temporal jitter and power masking via a post-compilation assembly-level patching utility. Experimental results demonstrate that the proposed countermeasure introduces a manageable memory overhead of $\mathbf{1 2. 0 \%}$ with no impact on RAM utilization and execution efficiency. Most significantly, the defense reduces the Bit Success Rate (BSR) to the theoretical minimum of 50.00% and increases the Hamming Distance to 32 bits, making key recovery statistically equivalent to random guessing under SPA attacks. These findings suggest that assembly-level hybrid hardening provides an effective and low-cost solution to secure the next generation of post-quantum satellite uplinks on ARM Cortex-M4 platforms against physical side-channel adversaries.