DTRRS: A Dynamic Task Real-Time Reconfiguration and Scheduling Architecture for FPGAs in Embedded Systems

A Configurable FPGA SIMD architecture for FSM-oriented software testing acceleration

Research on real-time Linux system modification and FPGA-based hardware-in-the-loop latency testing

With the increasing demand for operating system determinism in fields such as industrial automation and high-frequency trading, it is difficult for general-purpose Linux systems to meet microsecond-level control requirements due to the nonreal- time nature of their scheduling strategies. This paper proposes a Linux kernel real-time modification scheme based on the PREEMPT_RT patch and optimizes user-space system call overhead by combining VDSO (Virtual Dynamic Shared Object) technology. To overcome the limitations of pure software testing methods in terms of clock accuracy and system load interference, this paper innovatively designs a "Hardware-in-the-Loop" (HIL) latency testing method based on a PCIe interface FPGA board. This method uses the FPGA onboard 125MHz high-stability crystal oscillator as an independent time base to periodically read and verify the hardware counter through the kernel high-resolution timer, accurately quantifying the system scheduling jitter. Experimental results show that under the Fully Preemptible mode, the system's scheduling latency in multi-tasking loads is significantly reduced, meeting hard real-time application requirements.

In-Hardware Fault-Tolerance Controller for Multi-FPGA Clustered Architectures

The growing adoption of Commercial-Off-the-Shelf (COTS) components in space applications necessitates addressing performance and reliability challenges in radiation-intensive environments. Field-Programmable Gate Arrays (FPGAs), widely employed in these systems, offer exceptional computational capabilities but are vulnerable to radiation-induced faults, such as Single Event Upsets (SEUs), which can cause unpredictable behavior or even system failure. This paper presents a solution for enhancing the reliability of FPGA cluster-based systems through two custom-designed hardware solutions, the beacon controller and the robust bus, as well as error correction and workload redirection mechanisms. They have been integrated into an FPGA computing cluster for space telecommunication applications and tested against radiation-induced effects by fault injection techniques and radiation test campaigns. Experimental results demonstrated that the proposed techniques significantly reduce the system downtime, achieving up to 99% system availability, and reduce the radiation-induced failure rate effects below 4%. These results validate the proposed mitigation strategies as a robust and reliable approach for ensuring system dependability in harsh environments, demonstrating excellent performance through a fully FPGA-based design that eliminates the need for external controllers, unlike most state-of-the-art solutions.

Cut Topology-Based FPGA Logic Architecture with Powerful Logic Capacity and Area Efficiency

Field-programmable gate arrays (FPGAs) have been an efficient alternative of implementation for digital circuits. Look-up table (LUT)-based programmable logic blocks (PLBs) serve as the foundation for FPGAs. As increasing the LUT input number to improve performance and logic capacity will introduce exponential area overhead, substantial research has focused on designing more efficient logic architecture. Previous approaches primarily design dedicated hardware by analyzing the frequency distribution of Boolean functions and implementing those with high frequency. However, these approaches face scalability challenges due to the explosive growth in the function space. In this paper, we consider the topology of cuts rather than Boolean functions they represent. By identifying topologies that occur commonly in cuts and integrating them with LUTs, we propose a new 8-input PLB architecture, named FLAIC. This architecture incurs only a slight area overhead compared to a 6-LUT while achieving logic capacity comparable to that of an 8-LUT. Post-synthesis results on VTR and Koios benchmarks demonstrate that FLAIC reduces the logic levels by over 20% compared to 6-LUTs. Additionally, post-implementation results show improvement in critical path delay by 11.9% and reduction in the number of Configurable Logic Blocks by 1.5% without sacrificing routability, compared to Intel Stratix 10-like architecture

Design and FPGA Implementation of a Low-Power Leakage-Aware Digital Processing Unit

Abstract The increasing demand for energy-efficient digital systems in portable, embedded, and Internet of Things (IoT) applications has made low-power design an important objective in modern VLSI and FPGA-based systems. This work presents the design and FPGA implementation of a Low-Power Leakage-Aware Digital Processing Unit (DPU) using Verilog HDL. The proposed architecture incorporates leakage-aware design techniques such as enable-controlled functional blocks, clock-enable based operation, and selective activation of processing modules to minimize unnecessary switching activity and reduce overall power consumption. The Digital Processing Unit performs fundamental arithmetic and logical operations while dynamically controlling inactive circuit sections to improve energy efficiency. The design is modeled at the Register Transfer Level (RTL), simulated for functional verification, and synthesized using the Xilinx Vivado design environment. Performance evaluation is carried out in terms of power consumption, resource utilization, timing characteristics, and operating frequency. Experimental results demonstrate that the proposed leakage-aware architecture achieves lower power dissipation compared to conventional processing units while maintaining reliable computational performance. The combination of low-power operation, efficient hardware utilization, and FPGA-based implementation makes the proposed design suitable for battery-operated devices, edge computing systems, and real-time embedded applications. Keywords: Low-Power Digital Processing Unit (DPU), Leakage-Aware Design, FPGA Implementation, Verilog HDL, Energy-Efficient VLSI.

An Extensive Analysis of Techniques and Developments in the Progress of RISC-V Customization and Hardware/Software Co-Design

Co-designing hardware and software and customizing Reduced Instruction Set Computer-V (RISC-V) have become important strategies for maximizing computer systems' performance, adaptability, and resource efficiency. Architectural review, neural network-based partitioning, and reconfigurable array designs are some of the major developments in the field of co-design concepts explored in this research work. The major advances in parallel computing and automation of the design process include the Adaptive Dataflow Architecture for Processing and Training Optimization (ADAPTO) array, Configurable Tagged Memory Extension (COMET) technique, and Kahn Process Networks. Dynamic micro-decoders, unique instruction set, and vector extensions for Artificial Neural Network (ANN) optimization are a few of the important developments in this area. It comprehensively compares the performance improvement, resource usage, and design automation framework that overcomes the current constraints for the broadening of RISC-V applications to many computing domains. The paper also underlines some state-of-the-art techniques. Current innovations enable us to realize a number of new technologies, which utilize advanced techniques, such as hardware-software co-design; adaptive pipelines; and intelligent memory management, leading to greatly enhanced computation efficiency. A number of the new methods being studied for both AI and edge computing are: custom neural processors, low-power accelerators, automated high-level synthesis tools, etc., all providing alternate means to meet increasing requirements for AI and edge computing use. All of these factors contribute to improved performance, lower latencies, and optimized use of resources and therefore, place RISC-V processing architectures as being the preferred architecture for the Intelligent Computing Solutions of the future.