Design and FPGA Implementation of a Low-Power Leakage-Aware Digital Processing Unit
TL;DR
The proposed architecture incorporates leakage-aware design techniques such as enable-controlled functional blocks, clock-enable based operation, and selective activation of processing modules to minimize unnecessary switching activity and reduce overall power consumption.
Abstract
Abstract The increasing demand for energy-efficient digital systems in portable, embedded, and Internet of Things (IoT) applications has made low-power design an important objective in modern VLSI and FPGA-based systems. This work presents the design and FPGA implementation of a Low-Power Leakage-Aware Digital Processing Unit (DPU) using Verilog HDL. The proposed architecture incorporates leakage-aware design techniques such as enable-controlled functional blocks, clock-enable based operation, and selective activation of processing modules to minimize unnecessary switching activity and reduce overall power consumption. The Digital Processing Unit performs fundamental arithmetic and logical operations while dynamically controlling inactive circuit sections to improve energy efficiency. The design is modeled at the Register Transfer Level (RTL), simulated for functional verification, and synthesized using the Xilinx Vivado design environment. Performance evaluation is carried out in terms of power consumption, resource utilization, timing characteristics, and operating frequency. Experimental results demonstrate that the proposed leakage-aware architecture achieves lower power dissipation compared to conventional processing units while maintaining reliable computational performance. The combination of low-power operation, efficient hardware utilization, and FPGA-based implementation makes the proposed design suitable for battery-operated devices, edge computing systems, and real-time embedded applications. Keywords: Low-Power Digital Processing Unit (DPU), Leakage-Aware Design, FPGA Implementation, Verilog HDL, Energy-Efficient VLSI.