Low-Power FPGA-Based Matrix Multiplier Using FSM-Controlled MAC Architecture

Abstract

In this paper, the design and FPGA implementation of the proposed 4×4 energy-efficient Matrix Multiplication Accelerator based on Finite State Machine controlled Multiply-Accumulate architecture are presented. The implemented architecture enables efficient arithmetic operations via iterative MAC execution under sequential control operation. The presented solution provides efficient computations by means of utilizing minimal amount of FPGA hardware resources. The architecture is implemented via RTL modeling based on Verilog/System Verilog. Functional verification was accomplished using simulation to validate proper operation and arithmetic computations within all computation steps. The implementation process includes RTL synthesis, placement and routing, and timing analysis as well as FPGA-based deployment of the accelerator using Xilinx Vivado environment. Proper functionality verification revealed correct arithmetic computations and matrix multiplication operation for the implemented accelerator. After implementation and timing analysis were performed; proper timing closure was achieved with on-chip power consumption of 0.136 W and chip junction temperature of 26.6 °C. The implemented architecture utilizes only 426 LUTs, 876 flip-flops, and 16 DSP48 slices while requiring no BRAM resources. Compared to other FPGA-based accelerators, implemented matrix multiplication accelerator provides more power-efficient implementation with lower thermal dissipation and efficient computational capabilities.