When Timing is Uncertain, Infer: Probabilistic Early FPGA Timing Analysis for Robust Critical Path Optimization

Abstract

Early-stage FPGA timing analysis is inherently uncertain: routing is incomplete, congestion is only partially observed, and interconnect delays are coarsely estimated. Despite this, timing-driven placement relies on deterministic static timing analysis (STA), whose max-based propagation enforces hard path selection and discards competing near-critical paths. We replace this propagation with a probabilistic formulation that models arrival times as random variables and approximates max operations using Gaussian moment matching, preserving multi-path competition. Integrated into VTR as a drop-in timingevaluation layer, the method requires no modification to the placement algorithm and remains compatible with existing optimizers. Across the VTR 7.0 benchmark suite, the method achieves a 6.05% geometric-mean reduction in critical path delay (CPD), reduces seed-dependent CPD variation by 60.9%, and incurs a 5.11% total-flow runtime overhead.