Sep 2026· IEEE Transactions on Parallel and Distributed Systems· Vol 37, pp. 2050-2064· 0 citations· 60 references
Computer Science
Abstract
Training GNNs on large-scale graphs imposes significant memory constraints for storing substantial amounts of graph structures and node features. This often necessitates the use of memory extensions such as SSDs, leading to a memory hierarchy with disparities in capacity and access speed. Existing approaches focus on mitigating the read amplification of SSDs used as memory extensions to enhance overall performance. However, these methods fail to achieve optimal performance on heterogeneous memory architectures such as DRAM–NVM systems and overlook the efficient utilization of fast memory. In this paper, we propose Malope, an efficient memory-aware and locality-preserved GNN training framework designed for heterogeneous memory systems. First, Malope introduces a memory-aware graph partitioning strategy that preserves multi-hop connectivity and maximizes fast memory utilization. Second, Malope presents a novel locality-preserved GNN training mechanism that reorganizes mini-batches to enhance data locality, thereby improving fast memory hit rates and minimizing partition switching overhead. Additionally, Malope integrates pipelined GNN training and partition switching to minimize data transfer overhead under low bandwidth conditions. Lastly, Malope enables fine-grained model persistence, built on reorganized mini-batch training, for rapid failure recovery. Experimental results on large real-world datasets show that Malope significantly outperforms state-of-the-art GNN training frameworks, achieving an impressive average speedup of <inline-formula><tex-math notation="LaTeX">$1.51\times$</tex-math><alternatives><mml:math><mml:mrow><mml:mn>1</mml:mn><mml:mo>.</mml:mo><mml:mn>51</mml:mn><mml:mo>×</mml:mo></mml:mrow></mml:math><inline-graphic xlink:href="cheng-ieq1-3705364.gif"/></alternatives></inline-formula>.
FAST is presented, a holistic framework that accelerates end-to-end TGNN training by jointly optimizing sampling, memory I/O, and computation and designs thread-efficient graph operators tailored to sparse temporal subgraphs, improving GPU cache locality and reducing the latency of aggregation and edge softmax.
This paper proposes LayUp, a layer-wise training optimization framework for edge devices with unified memory architectures that achieves speedup and energy reduction compared to baseline GPU-only training for GPT-2 models on the NVIDIA Jetson Orin NX, while conventional offloading increases latency.
Bang-San Lee, Young-Ho Gong· Proceedings of the ACM/IEEE...· 0 citations
Xema is presented, a memory-efficient diffusion serving system that exploits predictable tensor lifetimes for trace-guided memory optimization and introduces an offline planner that jointly selects parallelism, concurrency, and memory control under GPU memory and SLO constraints.
Xueze Kang, Guangyu Xiang, Suyi Li et al.· 1 citation
This paper introduces a novel chunk-based graph representation model, featuring classified and hierarchical vertex storage and chunk layout optimization, to improve I/O utilization and presents a latency-optimized access mechanism featuring user-space asynchronous I/O execution and hotness-aware chunk caching management to accelerate I/O and boost cache efficiency.
Rui Wang, Weixu Zong, Shuibing He et al.· ACM Transactions on Storage· 0 citations
Compute-in-memory (CIM) architectures mitigate the von-Neumann bottleneck by embedding computation directly within memory crossbars, delivering order-of-magnitude improvements in energy efficiency and throughput. Among the emerging technologies, non-volatile-memory (NVM)-based CIM is particularly attractive owing to its non-volatility, ultralow standby power, and high integration density. Nevertheless, capacity-constrained NVM crossbars can accommodate only a fraction of a deep neural network's weights at any instant, necessitating frequent reprogramming that incurs substantial latency and energy penalties. We observe that the problem of scheduling weight updates onto such a limited-capacity crossbar is isomorphic to a bipartite-graph assignment problem. Motivated by this insight, we propose a static scheduling framework that systematically minimizes reprogramming cost. The framework comprises three synergistic stages: (i) bipartitegraph-driven row- and column-reordering formulated as an optimal assignment problem; (ii) fine-grained bit-flip minimization guided by hardware-aware correction logic; and (iii) a prioritydriven consolidation layer that allows designers to favor either energy or latency. Evaluations conducted on a customized STT-MRAM CIM simulator demonstrate an average 41% reduction in programming energy, an average 19% reduction in latency, and a 49% improvement in the energy-delay product over the conventional baseline.
Can Gao, Xuejin Li, Kaiwei Zou et al.· IEEE Non-Volatile Memory Sys...· 0 citations
PFM (PIM-as-Flexible-Memory), a dual-view memory system that decouples physical data layout from accessor-visible logical views, is presented, demonstrating its effectiveness and broad applicability as a unified memory management solution for NPU-PIM systems.
Shixin Zhao, Lian Liu, Tian Han et al.· 0 citations
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