Dual Threshold Based Low Power MAC Unit for Convolution Operations
TL;DR
A low-power MAC architecture is presented, where both the multiplier and adder blocks are constructed using a dual-threshold voltage (Dual-Vth) full adder, and simulation results demonstrate a substantial reduction in leakage power compared to conventional MAC designs.
Abstract
The growing demand for portable and high-performance computing systems has intensified the need for low-power VLSI designs. Among various digital signal processing (DSP) components, the Multiplier Accumulator (MAC) unit plays a crucial role in applications such as filtering, convolution, and image processing. However, MAC operations consume a significant portion of total power, especially when implemented using conventional arithmetic circuits. In this work, a low-power MAC architecture is presented, where both the multiplier and adder blocks are constructed using a dual-threshold voltage (Dual-Vth) full adder. The proposed design effectively minimizes leakage power while maintaining computational accuracy and performance. The MAC unit is employed for convolution operations, including periodic and 2D convolution, and simulation results demonstrate a substantial reduction in leakage power compared to conventional MAC designs. This method emphasizes the role of transistor-level design optimizations in improving the energy efficiency of DSP while preserving both speed and accuracy.