A systematic methodology to convert a trained DWSNN into an equivalent Spiking Neural P (SN P) system, a biologically-inspired, rule-based computational model drawn from membrane computing, by extracting symbolic firing rules from the hidden-layer spike activity is proposed.
Abstract
Distributed wireless spiking neural networks (DWSNNs) are a promising paradigm for energy-efficient edge inference in resource-constrained environments such as wireless sensor networks (WSNs). Yet, two limitations persist: their internal decision process is opaque, and their residual energy footprint remains a limiting factor for ultra-low-power deployments. This paper proposes a systematic methodology to convert a trained DWSNN into an equivalent Spiking Neural P (SN P) system, a biologically-inspired, rule-based computational model drawn from membrane computing, by extracting symbolic firing rules from the hidden-layer spike activity. The resulting SN P system provides direct, human-readable decision explanations while consuming three orders of magnitude less energy than its parent SNN. Experiments on the Neuromorphic MNIST (N-MNIST) dataset with a two-layer fully connected SNN using phase encoding and Leaky Integrate-and-Fire (LIF) neurons show that the SN P system retains approximately 84% of the original classification accuracy (73.77% vs. 87.68%) while the output layer connectivity decreases from 1000 to 120 class-specific connections. This complexity reduction is governed by a parameter related to the number of relevant hidden neurons per class that can be chosen according to a trade-off between computational complexity reduction and output accuracy. These results position SN P systems as lightweight, interpretable surrogates for trained distributed wireless SNNs in neuromorphic edge deployments.
An in depth analysis of the different trade-offs between quantization, generalization performance, and energy efficiency between binary SNNs, multi-level SNNs and ANNs for two different applications scenarios: image classification and image denoising and results show that multi-level spiking neurons provide better information compression, allowing therefore a reduction in latency without performance loss for classification tasks.
A. Castagnetti, Alain Pegatoquet, Benoît Miramond· IEEE Journal on Selected Are...· 0 citations
Energy-efficient neuromorphic computing at the edge requires simulation tools that can capture the non-ideal behavior of mixed-signal spiking neural network (SNN) hardware while supporting system-level design exploration. This work presents an open-source hardware-aware simulation framework for mixed-signal SNNs that enables comparative analysis across neuron, synapse and architecture choices. The framework supports multiple neuron models, including Leaky Integrate-and-Fire (LIF), Hodgkin-Huxley (HH) and Axon-Hillock (AH), together with non-volatile analog synapses based on floating-gate transistors and ReRAM devices. By incorporating device-level nonlinearities directly into PyTorch-based training and inference, the tool enables optimization of physical synaptic parameters rather than idealized abstract weights. The framework is evaluated on standard neuromorphic benchmarks, including N-MNIST, DVS Gesture and Spiking Heidelberg Digits (SHD). For each model dataset configuration, it reports classification accuracy together with hardware-oriented metrics such as silicon area, power consumption and quantization sensitivity. These capabilities enable cross-layer design space exploration and help identify neuron-synapse configurations that best satisfy application-specific constraints on accuracy, energy efficiency, area and hardware fidelity.
Sayma Nowshin Chowdhury, V. Nair, Taseen Forhad et al.· 0 citations
Energy efficiency is a key constraint for deploying machine learning models on resource-limited internet of things (IoT) and edge devices. Spiking Neural Networks (SNNs) are often proposed as an energy-efficient alternative to conventional Artificial Neural Networks (ANNs) due to their event-driven computation paradigm. However, direct and fair energy comparisons between SNNs and ANNs on inexpensive general-purpose microcontrollers remain limited. In this work, we present a controlled experimental comparison of inference-time energy consumption between an SNN and an ANN with identical multilayer perceptron architectures deployed on an ESP32-C6 microcontroller. Both networks are implemented in C/C++ without relying on optimized inference libraries, use int8 quantization, and are evaluated on the MNIST dataset. Energy consumption is measured directly during inference under identical implementation and measurement conditions to isolate the impact of the computational paradigm. Quantitatively, the ANN requires 11.01 mJ per inference, whereas the SNN consumes 2.31 mJ, 2.34 mJ, and 3.88 mJ for 1, 3, and 10 simulation timesteps, respectively. This corresponds to an approximate reduction in energy consumption of about [Formula: see text] for a single timestep and still about [Formula: see text] even at ten timesteps, demonstrating that the SNN maintains a substantial efficiency advantage under the evaluated conditions. These findings indicate that spiking neural networks can provide significant inference-time energy savings on widely available microcontroller units even without specialized hardware acceleration, while emphasizing the importance of controlled and reproducible comparison conditions.
Jonas Hansert, Franck Gechter, Peter Offermann· International Journal of Neu...· 0 citations
Spiking Neural Networks (SNNs) are promising for low-power edge intelligence due to their event-driven computational model. However, their hardware implementation poses challenges in terms of energy efficiency and memory access overhead. This paper presents an SRAM-based near-memory computing neuromorphic core supporting 256 leaky integrateand-fire neurons and 65,536 synapses. Synthesized in 40 nm low-power CMOS, the core occupies 0.3 mm2, operates at 70 MHz, consumes 7.67 mW, and achieves $\mathbf{0 . 6 4} \mu \mathbf{J}$ per inference and 0.22 pJ per synaptic operation. A five-core SNN system reaches 96% accuracy and 11 kFPS throughput on the MNIST dataset. A complete System-on-Chip was fabricated using SkyWater 130 nm CMOS via the eFabless multi-project wafer platform, including a small programmable computing core interfaced with a RISC-V processor via the Wishbone bus as a standard memory-mapped peripheral. This core implements 32 neurons and 8,192 synapses, and occupies 0.33 mm2 within a total chip area of 7 mm2. Firmware was loaded onto the SoC to verify the functionality of the full hardware-software system. Measurement results confirm improved energy efficiency and real-time performance, highlighting the suitability of SRAM-based architectures for ultra-low-power neuromorphic computing at the edge.
Linh Nguyen-Phuong, Chi Hoang Phuong, Anh Ong-Tung et al.· IEEE International Conferenc...· 0 citations
Energy consumption is becoming one of the main constraints for neural network inference on edge devices, where compute, memory, and power budgets are tight. A large number of works already study the efficiency of Deep Neural Networks (DNNs), and a growing body of work does the same for Spiking Neural Networks (SNNs). However, comparing the two on equal terms is not straightforward because existing analyses rarely rely on a shared decomposition of inference energy linked to the actual hardware behavior. This Mini Review synthesizes hardware-aware studies into a unified taxonomy that decomposes inference energy into seven contributions: computation Ecompute, memory access Ememory, internal state Estate, temporal processing Etemporal, activation Eactivation, static leakage Eleakage, and clock distribution Eclock. The corresponding expressions are derived from classical CMOS energy models and interpreted using representative findings from hardware studies. We illustrate the taxonomy using representative studies on microcontrollers, FPGAs, ASICs, and neuromorphic processors. The objective is not to recommend one paradigm. It is to provide a reading grid close to the hardware that can support architectural choices when energy, accuracy, and latency cannot all be optimized at once.
Mohamed El-Hafci, M. A. Sabri, A. Aarab· Frontiers in Neuroscience· 0 citations