An extensible FPGA-based real-time correction processor for 1024 × 1024 infrared focal plane arrays

Abstract

Large-format infrared focal plane arrays are increasingly used in remote sensing, industrial inspection, night-vision imaging, and other scenarios that require wide-field perception and stable image acquisition under complex conditions. As the detector format continues to expand, real-time infrared imaging systems must process a rapidly increasing amount of raw data while maintaining low latency, moderate hardware consumption, and reliable system operation. For a 1024×1024 infrared detector, the main challenge is therefore not only to implement image correction algorithms, but also to establish a hardware-oriented processing architecture that can support continuous dataflow, flexible calibration, and practical system verification. This paper presents an extensible FPGA-based real-time correction processor implemented on the Xilinx Zynq UltraScale+ MPSoC ZCU104 platform. The proposed processor focuses on two major non-ideal characteristics of infrared detector outputs: dark current drift and fixed pattern noise. To improve image uniformity, dark current correction and fixed pattern noise correction modules are designed and integrated into a streaming processing pipeline. The corresponding dark current matrix and pixel gain matrix are obtained through dark-field measurement and standard light source calibration, providing experimentally supported correction parameters for the imaging system. By emphasizing hardware-friendly correction rather than computation-intensive image enhancement, the design achieves a balance between correction effectiveness and resource efficiency. To enhance system flexibility, an AXI bus interface is introduced for parameter configuration, mode switching, and processing control. This allows calibration parameters to be updated offline during the experimental calibration stage, while the real-time imaging pipeline remains stable during normal operation. In addition, a DDR-based debugging path is incorporated to export both raw and corrected image data, enabling data comparison, image quality evaluation, and system-level verification. The corrected grayscale images are finally transmitted through an HDMI interface for real-time visualization. The proposed architecture also shows a clear throughput margin at the algorithmic pipeline level. Under a one-pixel-per-clock streaming assumption, the correction pipeline has a theoretical processing upper limit of approximately 95 fps at a100 MHz processing clock for 1024 × 1024 images. This indicates that the correction pipeline itself is not the dominant bottleneck in the current design; instead, the end-to-end frame rate is more closely related to front-end acquisition, buffering strategy, and system-level data scheduling. Experimental results show that the processor can stably complete real-time correction, debugging output, and display with low hardware overhead. Moreover, its modular streaming pipeline, AXI-based configuration mechanism, and DDR-assisted debugging path allow the system to be extended to different detector formats, calibration conditions, and processing requirements. Therefore, the proposed processor is suitable not only for the present FPGA prototype, but also for future large-format infrared imaging platforms and ASIC- oriented system integration.