Power Consumption Bottlenecks and Materials Innovation Pathways for Silicon-Based Logic Devices in the Post-Moore Era
Abstract
As silicon-based CMOS logic devices continue to scale down, problems such as short-channel effects, quantum tunneling, and the subthreshold swing limit are becoming increasingly pronounced. Power consumption has become a key factor affecting chip performance, thermal management, and energy efficiency. This paper presents a systematic literature review to analyze the power consumption mechanisms of silicon-based logic devices and the associated material-level factors. It reviews the major challenges faced by conventional silicon, gate dielectrics, strained silicon, and interconnect materials in low-power applications, with emphasis on potential solutions including high-mobility channel materials, high-k gate dielectrics, heterogeneous integration structures, low-resistance interconnect materials, and high-efficiency thermal management materials. It also discusses opportunities for materials innovation in the post-Moore era. The review indicates that, under advanced process conditions, device-structure optimization alone cannot adequately meet power-control requirements, whereas materials innovation may provide new technological pathways to improve device energy efficiency. Emerging materials, including high-k dielectrics, two-dimensional semiconductors, carbon-based materials, and ferroelectric materials, offer promising opportunities to reduce leakage current, optimize operating voltage, and enhance energy efficiency. This paper provides a theoretical foundation for the design of low-power integrated circuits and semiconductor materials research.