Emerging Nanoelectronic Technologies for Next-Generation VLSI: Devices, Challenges, and Prospects

Abstract

The continuous scaling of CMOS technology enables significant progress in performance and integration density in VLSI. However, due to short-channel effects, leakage currents, interconnection delays, variability effects, and power-density limitations, at the current sub-5 nm feature size, the conventional scaling down of CMOS is becoming more and more challenging. This research work discusses a few promising nanoelectronic devices beyond the conventional CMOS, such as CNTFETs, TFETs, nanowire FETs, SETs, graphene-based devices, and spintronic devices. The principle of operation, characteristics, scalability, CMOS compatibility, and perspectives of VLSI application of the devices under consideration are comparatively analyzed. Possible problems related to the integration of the devices, including fabrication scalability, device variability, process complexity, cost, reliability, and thermal issues, are discussed. It is shown that heterogeneous and monolithic 3D integration can be effective methods for combining special-purpose nanoelectronic devices with traditional CMOS technology. Perspectives related to the application of 2D materials and negative-capacitance devices are discussed.