Localization of Gate Oxide Defects within Pool Capacitors in NAND-type 3D Flash Memory

Abstract

As NAND-type 3D Flash memory continues to scale in performance, speed, and storage density, the underlying architecture has grown significantly more complex. Global reference signals and clock networks must traverse large areas of the chip while driving numerous loads. A defect affecting even a single load can disturb the integrity of the shared global signal, causing degradation across multiple functional blocks and potentially resulting in fatal system-level failures. Therefore, rapid and accurate localization of defects on these global signal paths is critical for root cause identification and for enabling design, layout, and process teams to collaborate to reduce DPPM and improve overall yield. In this work, we demonstrate the localization of a subtle defect within the pool capacitor of a global signal line in a NAND-type 3D Flash memory device. This type of defect is challenging to detect due to its small physical footprint and its location buried deep within the die, which makes typical OBIRCH hotspots diffused or smeared out. The methodology presented here enables precise identification of such hidden failures.