Improving chip macro placement via GFlowNet-guided tree search
TL;DR
Experiments demonstrate that FlowPlace consistently outperforms strong RLbased and search-based baselines, achieving up to 8.4% HPWL reduction on ISPD2005 benchmarks, which highlights the potential of flow-based generative models as a powerful foundation for next-generation learning-driven EDA tools.
Abstract
This study addresses the long-standing challenge of a core task in chip physical design, termed macro placement. The problem is characterized by an enormous combinatorial search space and a highly multimodal cost landscape. While recent learning-based approaches have shown promise, reinforcement-learning rollouts often suffer from mode collapse and insufficient exploration, limiting their effectiveness when integrated into tree-search frameworks. In this work, we propose FlowPlace, a bi-level optimization method that couples global tree search with a Generative Flow Network (GFlowNet)—a class of probabilistic generative models designed for sampling structured objects in proportion to their rewards. FlowPlace retains the directed exploration benefits of tree-based search while leveraging the inherent multimodal sampling ability of GFlowNets to produce diverse, high-quality placements from frontier states. To enable stable trajectory generation in long-horizon placement tasks, we introduce a hybrid reward formulation combining terminal wirelength metrics with incremental stepwise contributions, along with a feasibility- and connectivity-aware action representation. Experiments on standard macro-placement benchmarks demonstrate that FlowPlace consistently outperforms strong RLbased and search-based baselines, achieving up to 8.4% HPWL reduction on ISPD2005 benchmarks. These results highlight the potential of flow-based generative models as a powerful foundation for next-generation learning-driven EDA tools.