BHARAT-TPM: Design and ASIC Implementation of an SPI Based AXI Enabled AES Accelerator

Abstract

Trusted Platform Modules (TPMs) serve as hardware roots of trust in secure System on Chip (SoC) environments, supporting essential security services such as secure key exchange, digital signatures, authentication, and cryptographic key management. Standalone validation of cryptographic hardware accelerators is an essential step for ensuring functional correctness before their integration into secure SoC platforms. Existing SPI and AXI based interface architectures primarily focus on communication and processor integration, with limited support for reusable pre-integration validation of cryptographic IP cores. This paper presents a SPI to AXI hardware validation framework for standalone verification of AXI enabled AES accelerators. The proposed architecture employs a structured packet based communication mechanism with dual clock domain synchronization and FIFO based buffering to enable reliable data transfer between the SPI interface and the AXI based AES accelerator. The framework supports AES encryption and decryption for all standard modes of operation with variable key sizes. The design is functionally verified using NIST SP 800-38A reference test vectors, and validated on a Xilinx Virtex UltraScale VCU108 FPGA, achieving an operating frequency of 333.33 MHz, utilizing 925 slices, and delivering a throughput of 46.9 Gbps. ASIC synthesis using the SCL 180 nm further demonstrates the feasibility of the proposed architecture for hardware realization. The proposed framework provides a validation platform that enables independent verification of AXI based cryptographic accelerators before their integration into the RISC-V based BHARAT-TPM.