An Area-Efficient CNN Accelerator for Handwritten Digit Recognition on FPGA-Based Edge Systems

Abstract

This paper describes a compact convolutional neural network (CNN) accelerator for handwritten digit recognition on the Xilinx PYNQ-Z2 platform. The proposed network architecture comprises two shallow convolutional layers (2 filters each) and two fully connected layers (12 neurons, then 10 neurons), with exactly 4,936 trainable parameters. We employ post-training quantization to 8-bit fixed-point precision (Q0.7 format for activations, Q4.3 for weights), achieving a test accuracy of 98.05% on the MNIST dataset with less than 0.15% accuracy loss relative to floating-point inference. The hardware implementation consumes 5,258 LUTs (9.9% of available), 3,809 flip-flops (3.6%), 2 BRAMs (1.4%), 6 DSPs (2.7%), and 1.669 W on-chip power with an end-to-end inference latency of 10.2 ms at 100 MHz, achieving a $12.4 \times$ speedup over software execution on the ARM Cortex-A9. The design demonstrates that compact CNNs with aggressive quantization enable viable edge AI inference on lowcost Zynq-7000 devices.