A VCMA-MTJ-Based Architecture for In-Memory Unified High-Reliability CAM and PUF Operations

Abstract

This paper proposes a Content-Addressable Memory (CAM) architecture relying on a twelve-transistor (12T) cell integrating two Voltage-Controlled Magnetic Anisotropy Magnetic Tunnel Junctions (VCMA-MTJs) targeting high-reliability Ternary CAM (TCAM) and Physically Unclonable Function (PUF) operations. The proposed 12T-2VCMA-MTJ cell comprises a voltage divider network (VDN), a sensing network (SN), and a match line network (MLN). In particular, the VDN is designed to ensure reliable search operations. The SN consists of a three-state buffer properly sized to well distinguish the match and mismatch cases, as well as to dramatically reduce the stand-by energy consumption. Finally, the MLN is composed by an NMOS transistor with the aim of eventually discharging the match line (ML) during the mismatch cases within the search operations. In the proposed architecture, PUF bits are generated by comparing the ML discharge time between two cells belonging to the same row of two different arrays by means of an arbiter. To improve the raw PUF stability, a remapping scheme aiming at dramatically reducing the chance of having unstable pairs is also implemented. The solution was validated through extensive post-layout Monte Carlo simulations in 65-nm CMOS technology, while including a VCMA-MTJ compact model, whose results prove the effectiveness of the proposed solution in terms of reliability for both TCAM and PUF operations. Indeed, when employed as both BCAM and TCAM, a zero-search error rate (SER) is observed at nominal conditions (i.e., 1.2 V and $25~^{\circ } $ C) when considering the worst-case scenario at the TT corner. Finally, when employed as PUF, a zero-observed bit error rate (BER) at both golden key (GK) and different voltage and temperature (VT) conditions is achieved when considering both the proposed remapping scheme and a temporal majority voting (TMV).