Hardware-level data layout approach to mitigate the memory row conflicts on FPGA-based CNN accelerators
TL;DR
A hardware-level data layout technique using a memory-centric accelerator architecture that improves memory performance in FPGA-based CNN accelerators in a scalable and hardware-efficient manner without requiring a large computational burden.
Abstract
Memory row conflicts (MRCs) continue to be a major bottleneck that results in higher latency, ineffective double data rate (DDR) usage, and decreased effective bandwidth in field-programmable gate array (FPGA-based) convolutional neural network (CNN) accelerators. The majority of current effort focuses on computational optimization, frequently ignoring inefficient memory access. In order to reduce memory reference codes (MRCs), this research suggests a hardware-level data layout technique using a memory-centric accelerator architecture. In order to improve hit rates and row buffer locality, the architecture incorporates a dynamic cursor-based address mapping method that adjusts to different feature map sizes across CNN layers and a dual-DDR setup for concurrent data access. The experimental results on VGG16, YOLOv2, and AlexNet show an 18% reduction in MRCs, a 40% increase in throughput, and a 23% decrease in latency compared to state-of-the-art techniques. The design uses a Xilinx Kintex-7 FPGA with low power usage of 1.52 W. The suggested method improves memory performance in FPGA-based CNN accelerators in a scalable and hardware-efficient manner without requiring a large computational burden.