LLM-Guided Design Space Exploration for Neural Network Accelerators on FPGA

Abstract

Neural network deployment on FPGAs relies on compilation frameworks that automatically generate streaming dataflow architectures mapping neural layers to optimized HLS/RTL kernels. These frameworks require tuning layerspecific architectural parameters that govern the trade-off between resource utilization and inference throughput. However, even for small networks, the resulting design space is too large for exhaustive exploration. Existing design space exploration (DSE) strategies for parameter tuning rely on black-box optimization techniques that frequently evaluate area-infeasible or low-performing configurations, reducing search efficiency and solution quality. We propose an LLM-guided DSE framework that integrates domain knowledge into the exploration through structured prompts. Combining this knowledge with feedback from previous evaluations, the LLM progressively refines parameter ranges, steering a downstream optimization engine toward resource-feasible, high-performance subspaces. Experiments on three neural network benchmarks deployed with the FINN framework on two FPGA platforms achieve up to $4 \times$ higher throughput while reducing search time by up to $3.3 \times$.