Jul 2026· International Journal of AI Electronics and Nexus Energy· Vol 2, pp. 124-127· 0 citations· 1 references
TL;DR
A combined hardware-andalgorithm design that pairs a carefully regularized binarized neural network (BNN) with a compact, variable-precision FPGA processor to enable accurate, real-time object detection without relying on off-chip memory is proposed.
Abstract
Convolutional neural networks (CNNs) achieve strong accuracy in object detection, but their heavy computation and memory demands make them difficult to run on embedded and mobile hardware. This work proposes a combined hardware-andalgorithm design that pairs a carefully regularized binarized neural network (BNN) with a compact, variable-precision FPGA processor. A new building block called DenseToRes is introduced to reduce the accuracy loss usually caused by aggressive 1-bit quantization. The supporting processor stores the entire trained network in on-chip memory instead of external DRAM and performs its multiplyaccumulate (MAC) operations using an XNOR-based processing element that can flexibly handle 1-, 2-, 4- and 8-bit operand widths from one shared gate array. Implemented on a Xilinx FPGA, the design achieves real-time performance of 64.51 frames per second with 64.92% mean average precision (mAP) on the PASCAL VOC dataset, while consuming only 6.58 W. The results show that jointly optimizing network structure and hardware precision can enable accurate, real-time object detection without relying on off-chip memory.
A hardware-efficient object detection accelerator based on XNOR-driven variable-precision computation for real-time edge artificial intelligence that reduces arithmetic complexity, memory bandwidth, and power consumption while supporting scalable real-time object detection on FPGA-based edge platforms.
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