Sep 2026· IEEE Transactions on Very Large Scale Integration (vlsi) Systems· Vol 34, pp. 2873-2886· 0 citations· 50 references
Abstract
Edge devices capable of running artificial intelligence (AI) applications have seen a surge in demand for energy-efficient and high-throughput computation. In this study, a 22-nm edge–AI processor, incorporating an accelerator with error-free Booth-value-confined (BVC) multiprecision (MP) multiplier and near-memory computing (NMC), is introduced to accelerate neural networks (NNs). It has the following three major features. First, a BVC MP multiplier based on radix-8 Booth (R8B) is introduced to reduce computation complexity by prohibiting the “±3” cases and support error-free training on GPU without accuracy loss originating from the mismatch between training and deployment. A PE is built based on this multiplier for parallel computation with 82% power reduction and 70% area reduction. Second, the proposed NMC-friendly data flow supports efficient data reuse and hence reduces off-chip memory traffic. The data flow supports data reuse of up to 16 times, matching the number of PEs and enabling regular read and write patterns. Third, a hardware-aware layer-wise model deployment approach is proposed with a memory space contiguity-aware (MSCA) model reshape strategy, and a hardware-aware NN splitting and scheduling algorithm. The proposed MSCA strategy maximizes burst access, and the proposed algorithm achieves efficient computation with high data reuse and low memory access. This deployment approach can achieve a reduction in memory access latency of 16.6%–32.0%. Measurements on a 22-nm test chip demonstrate a peak power efficiency of 33.98 TOPS/W under synthetic full-PE-utilization conditions, while achieving 12.92–29.11 TOPS/W for end-to-end NN inference on DarkNet19, VGG16, ViT-Tiny, and ResNet34.
The increasing computational demands of artificial intelligence (AI) inference at the edge require hardware accelerators capable of overcoming the von Neumann bottleneck while operating under power constraints. Conventional digital architectures based on multiply–accumulate (MAC) units are limited in energy efficiency and scalability for resource-constrained applications. This work presents a proof-of-concept AI accelerator based on analog frequency–domain computation implemented within a semi-systolic array architecture. The proposed approach exploits frequency mixing to perform multiplication and accumulation operations in hardware, enabling the execution of matrix–matrix operations, which constitute the General Matrix Multiplication (GEMM) methods that dominate the computational workload of convolutional and fully connected neural networks. The proposed system consists of a custom printed circuit board controlled by an ATmega328P microcontroller(Microchip Technology Inc., Chandler, AZ, USA) and a software stack designed to interface with standard machine learning frameworks such as PyTorch. The software layer enables neural network operations, including convolutional and fully connected layers, to be mapped onto hardware-executed matrix–matrix computations through an abstraction analogous to the General Matrix Multiplication (GEMM) functionality provided by Level-3 Basic Linear Algebra Subprograms (BLAS). Matrix multiplication and accumulation are partly performed directly by the hardware processing elements, while the software control unit coordinates data movement and computation scheduling. Although bias operations are not implemented in the current prototype, their comparatively low computational cost makes them less critical to the overall acceleration strategy. A quantization-aware mapping methodology constrained by analog-to-digital and digital-to-analog converter specifications is introduced to translate neural network operations into frequency–domain computations. The paper further describes the hardware architecture, communication protocols, software stack organization, and interactions between system components. In addition, the effects of analog nonidealities and error sources associated with frequency–domain multiplication are investigated, and simulations of the proposed processing elements are presented to evaluate the computational approach. Experimental and simulation results demonstrate the feasibility of performing dense linear algebra operations through analog frequency–domain processing and validate the operation of the processing elements. The study further explores converter resolution, frequency interference, and analog component nonidealities and provides a comparison with conventional digital and other low-power accelerator approaches. The results indicate that exploiting the inherent parallelism of analog computation offers a promising pathway toward ultra-low-power AI inference, making the proposed architecture a potential alternative for energy-constrained edge applications.
Andrei Iliescu, O. N. Ionescu, Adrian Iosif· Electronics· 0 citations
Number Theoretic Transform (NTT)-based polynomial multiplication is a computationally intensive operation in lattice-based post-quantum cryptography (PQC) schemes such as CRYSTALS-Dilithium. Existing hardware accelerators optimize area and timing performance, without focusing on evaluating trade-offs among hardware utilization, execution latency, operating frequency, and power consumption. This article investigates such trade-offs through two lightweight field-programmable gate array (FPGA) implementations of an iterative NTT-based polynomial multiplication accelerator, namely non-pipelined and 4-stage pipelined architectures. Both implementations employ a single butterfly unit based on Cooley–Tukey and Gentleman–Sande configurations to compute the forward NTT (FNTT), inverse NTT (INTT), and coefficient-wise multiplication (CWM). The 4-stage pipelined architecture employs pipeline registers in the modular multiplication and Barrett reduction datapaths to maximize the operating frequency. Both architectures are implemented on an Artix-7 FPGA and evaluated across operating frequencies ranging from 10 MHz to 280 MHz. The results show that the non-pipelined architecture provides reduced hardware overhead and lower power consumption, whereas the pipelined architecture improves timing scalability and successfully operates at 280 MHz. At the maximum operating frequency, the pipelined implementation utilizes 1115 slices and achieves execution times of 4.58 μs, 0.93μs, and 4.58μs for FNTT, CWM, and INTT computations, respectively, with an average power consumption of 133 mW. The Area–Time Product (ATP) and Energy–Delay Product (EDP) evaluations demonstrate that the pipelined architecture achieves improved overall efficiency within the proposed lightweight single-butterfly-based polynomial multiplication architecture at higher operating frequencies, obtaining an ATP of 7.74×103 Slice-μs and EDP of 1501.52 nJ-μs.
Omar S. Sonbul, Muhammad Rashid, K. Khayyat et al.· Electronics· 0 citations
The fast advancement of deep neural networks has led to the escalation of hardware accelerator needs that achieve high functionality as they comply with strict requirements of power and latency, particularly in edge and embedded artificial intelligence. In this paper, the research introduce a low power, pipelined single-precision (32 bits) floating-point data path that is to be used in neural network accelerators compliant with the IEEE 754 single-precision standard. The suggested design uses multi-stage pipelining on addition, multiplication and accumulation units, which greatly decreases the critical path delays and enhances the overall throughput. Efficiency of power is also by ensuring that its techniques such as operand isolation, clock-conscious staging of pipelines and minimized switching activity in arithmetic units. The architecture has a combined optimization in latency, energy, and numerical accuracy, making it possible to infer the numerical accuracy of resource-constrained platforms in real-time. Simulations after synthesis show that the proposed data path has significant propagation delay and dynamic power improvements over the state-of-the-art non-pipelined floating-point implementations and can compute the accuracy needed by the deep learning workloads. Its scalable and modular design is flexible and can be easily adapted to other neural network designs. The findings demonstrate the strength of the targeted design towards addressing the increasing demand of high-performance, low-energy neural network hardware, which provides a viable approach to edge AI systems with severe demands on both power and performance.
K. Kalaichelvi, M. Deepika, M. Bhuvaneshwari et al.· International Conference Com...· 0 citations
Embedded systems increasingly require on-device deep learning, yet their processors must simultaneously handle real-time sensing, networking administration, and data control. Existing Field-Programmable Gate Array (FPGA) accelerators typically target peak per-operator throughput without addressing concurrent execution demands of real-time embedded platforms. This paper presents a systolic array-based accelerator prototype implemented on the Zynq-7000 SoC integrated directly into PyTorch, enabling dense linear algebra to be delegated to the FPGA chip while Cortex-A9 continues executing the software stack uninterrupted. Unlike traditional accelerators optimized for peak per-operator speed, this design prioritizes asynchronous co-executionbetween the processing system (PS, the dual-core Cortex-A9) and the programmable logic (PL): The PL performs tiled matrix multiplication, while the PS executes preprocessing, orchestration, and I/O data concurrently, increasing effective end-to-end throughput regardless of the relative isolated performance of CPU and FPGA. The proposed module includes high-level-synthesis (HLS)-based matrix multiplication, activation functions, and Advanced eXtensible Interface (AXI)-Stream Direct Memory Access (DMA) interfaces, wrapped as custom PyTorch kernels under the PetaLinux operating system. The results obtained on the PYNQ-Z2 board show that, once the DMA transfer time is included in the measurement, the FPGA path does not surpass Cortex-A9 in isolated per-operator latencies across the evaluated range; the benefit lies instead in delegating the matrix compute to the fabric at low incremental power while the host CPU cores stay available for concurrent tasks. A concurrent workload sweep across matrix sizes from 8×8 to 256×256 confirms that the co-execution mode sustains 98–99% of available PS compute throughput compared with a constant ≈50% in single-core blocking mode; the difference is statistically significant for all evaluated sizes (see Mann–Whitney U: U=25, p=3.97×10−3, perfect discrimination, n=5). A fair dual-core CPU-only baseline attains comparable PS availability, so this figure reflects the dual-core scheduling that co-execution enables rather than a per-operator advantage of the fabric; the accelerator’s distinct role is to perform the matrix arithmetic off the general-purpose cores at low incremental power. The design occupies only 8% of available look-up tables (LUTs) and 5% of digital signal processing (DSP) blocks, maintains 1.69 W power with a junction temperature of 44.5 °C, and achieves 96.10% MNIST accuracy under fixed-point arithmetic.
Omar Hernandez-Yañez, A. Juárez-Lora, J. Y. Montiel-Pérez et al.· Electronics· 0 citations
Edge artificial intelligence (Edge AI) has emerged as a promising solution to provide real-time and privacy-aware intelligent services at proximity to data sources. However, it is difficult to implement deep learning on edge devices with limited resources, such as microcontrollers, embedded devices, and IoT terminals with low power consumption, because they have limited computing power, memory capacity, and energy supply. This paper introduces a concise overview on AI compilation and hardware co-design methodologies for efficient inference execution on resource-constrained edge devices. This paper provides an overview of the key challenges in deploying deep learning models on resource-constrained devices and presents illustrative solutions in terms of compression techniques and hardware implementation. The discussion includes graph optimization, operator fusion, quantization, memory-aware inference, hardware-specific code generation, accelerator-based inference, latency prediction, and runtime optimization. The reviewed work suggests that high-performance efficient edge AI requires cross-layer rather than isolated model-level compression. AI compilation enables more efficient execution by converting neural networks to optimized hardware-aware code, and hardware- co-design further improves latency, memory, and energy efficiency. These results imply that next-generation edge AI systems should focus on portable compiler toolchains, memory-aware optimization, energy-aware design, and standardized benchmarking methodologies.
Chenhe Zhu· Applied and Computational En...· 0 citations
SRAM-based compute-in-memory (CiM) accelerators have emerged as a promising approach for low-power inference in edge devices by alleviating data-movement overhead. However, existing CiM designs face a fundamental trade-off: integer-based CiM suffers from limited numerical accuracy, while floating-point CiM incurs substantial energy and area overhead due to complex exponent handling and peripheral circuits. This paper presents an analog CiM accelerator based on the SMX6 format, which extends the block floating-point (BFP) representation with a lightweight microexponent (μE) shared by pairs of values. By embedding μE-aware scaling directly into the analog MAC operation, the proposed design achieves improved numerical fidelity without introducing costly digital shift-and-align logic. To further address accuracy degradation caused by analog dynamic-range limitations, the accelerator supports configurable block granularity, allowing the accumulation range to be adaptively adjusted to match layer-wise activation distributions and ADC input constraints. Implemented in 28nm CMOS technology, the proposed SRAM-based ACiM achieves accuracy close to the FP32 baseline across diverse workloads, while delivering up to 54.19 TOPS/W energy efficiency and 4.66 TOPS/mm2 area efficiency. These results demonstrate that micro-exponent-aware analog CiM with configurable granularity is an effective and practical design point for energy-efficient edge inference.
W. Han, Dohyun Kim, Jihoon Park et al.· Proceedings of the ACM/IEEE...· 0 citations
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