A DRA driver is presented that makes composable CXL memory a schedulable cluster resource, and the resulting shared-memory tier for cross-node KV-cache reuse in LLM serving is evaluated, demonstrating memory disaggregation rather than prefill/decode disaggregation.
Abstract
We present a Kubernetes Dynamic Resource Allocation (DRA) driver that makes composable CXL memory a schedulable cluster resource, and evaluate the resulting shared-memory tier for cross-node KV-cache reuse in LLM serving. The driver composes CXL regions on demand, materializes them as DAX devices on each participating host, and injects them into pods under a single Container Device Interface (CDI) name so that pods on different nodes access the same physical region. A shared-memory connector for vLLM/llm-d uses that region as a KV-cache tier with a slot directory embedded inside the shared medium, which eliminates the need for an external metadata service. On a two-node cluster with a 512\,GiB CXL appliance and Qwen2.5-7B-Instruct, cross-node prefix reuse reduces TTFT by 5.5$\times$--36.6$\times$ at an external hit rate of 95.4--99.5\,\%, while node-local tiers (GPU prefix caching, CPU-DRAM offload) fall back to full recompute. The sharing gap, defined as the latency ratio between cross-node and same-node reuse, is 1--4\%, indicating that cross-node reuse incurs little additional latency relative to same-node reuse on our testbed. Both replicas run full engines; the study demonstrates memory disaggregation rather than prefill/decode disaggregation. We report this as a feasibility study rather than a performance evaluation.
LM-CXD bridges the semantic gap between the serving engine and the device, and exposes NAND-to-DRAM progress to the serving engine, and uses device DRAM as a GPU-accessible buffer to hide NAND latency under limited device DRAM.
Hyunsun Chung, Taewan Noh, Minji Kim et al.· 0 citations
It is found that cache performance depends on transfer granularity, intermediate memory use, and when transfers enter the request schedule, not only on device bandwidth, not only on device bandwidth.
Joseph Kanichai, T. De Matteis, Animesh Trivedi· 1 citation
Results show that standardizing the host-interface layer reduces both the engineering cost of PIM simulator development and the energy overhead of simulation-driven workload evaluation, while reducing host CPU utilization and package energy by up to 50% on transfer-intensive workloads.
Large language model serving faces a critical memory bottleneck: the KV cache grows with sequence length and batch size. PagedAttention uses fixed-size memory blocks to reduce allocator-level fragmentation, but recent KV eviction algorithms operate at a token granularity finer than block-level management. This mismatch...
Yuanhang Gao, Xiangrui Yang, Yuan-Feng Chen et al.· 1 citation
On-device mobile Large Language Model (LLM) inference is gaining significant attention. However, mobile devices operate in highly dynamic multitasking environments where users frequently switch between applications. This creates memory pressure, forcing LLM memory (model weights and KV cache) to be evicted by the opera...
Hong Yu, Minsung Kim, Jongseok Park et al.· 0 citations
Borges is presented, to the authors' knowledge, the first fault-tolerant shared log whose data and ordering state reside in a DRAM/SSD hybrid device accessed with Compute Express Link (CXL).
Hao-Wei Chen, Yi-Ming Xiang, Zhi-Peng Jia et al.· Proceedings of the ACM SIGOP...· 0 citations
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