ReRAM-based in-memory computing (IMC) architectures enable efficient neural-network inference on edge devices, due to their high density and non-volatility. However, ReRAM is prone to the stuck-at faults (SAFs) which would distort weight mappings and reduce model accuracy substantially. To tackle this problem, a high-efficiency fault-resilient (HE-FR) framework is introduced in the paper, which couples layered-precision quantization based on the generalized gaussian distribution cumulative distribution function (GGD-CDF), preserving weight distributions with the minimal information loss. Further, a fault-aware weight re-decomposition method is proposed. Specifically, a Q-agent-based method is proposed for sparse SAFs, which employs offline reinforcement learning to construct a globally optimized hash table with reduced compilation complexity, while incorporating both weight matching and cell-state stability into the reward function to suppress electro-stress. For dense SAFs, we exploit a greedy search over the remaining cells to provide rapid and accurate mappings. Experimental results show that GGD-CDF quantization improves accuracy by 2.18% over Float32. Under fabrication faults, HE-FR surpasses a fault-free method by 12.97% and accelerates compilation by $197\times $ with only 0.024% picojoule-level energy overhead. In electro-stress evaluations, HE-FR reduces performance degradation by 46.27%. It demonstrates that the proposed framework has advantages in robustness, efficiency, and reliability.
Junlong Lin, Wenhua Wu, Mingtao Wang et al.· IEEE Transactions on Circuit...· 0 citations
Serving as catalysts for real-time insight, predictive intelligence, and autonomous decision-making, digital twin (DT) systems are driving transformation in industrial domains. In global logistics supply chains, the coupling of DTs with AI/ML, edge computing, and 5G/6G connectivity offers powerful capabilities for market volatility warning and risk detection. However, these advantages also introduce profound cybersecurity, privacy, and trust challenges. Existing standards such as ISO/ IEC 27000, 3GPP TS 33.501, and ITU-T Y. 3172 partly address generic security and AI frameworks, but lack specificity toward dynamic, AI-driven DT ecosystems. This paper presents a next-generation AI-driven digital twin framework tailored for logistics supply chains, emphasizing security, interoperability, and standard alignment. We map cross-layer threats to curated countermeasures, and evaluate their alignment with international standards. We analyze standardization gaps and propose extensions and new research directions for DT-aware AI governance, cross-domain interoperability, and real-time assurance. A case study on logistics volatility detection demonstrates how this framework supports resilient, trustworthy operations. Finally, we delineate a roadmap for standardization-driven secure DT ecosystems, aiming to guide practitioners, standard bodies, and researchers.
Static random-access memory (SRAM)-based computing-in-memory (CIM) macros have been widely studied to improve the energy efficiency of edge artificial intelligence (AI) inference tasks. However, less attention has been given to AI training, which requires CIM macros to not only perform matrix multiply-accumulate (MAC) operations but also support matrix transposition. To address the limitations of previous analog transpose and digital non-transpose SRAM CIM macros, this work features: 1) a cyclic-weight-mapping SRAM array that enables matrix transposition and reuse of MAC circuits during both feed-forward (FF) and back-propagation (BP) phases; 2) a digital CIM architecture employing signed fixed-point mantissa encode and a vector-wise pre-alignment (VWPA) scheme, supporting multiple data formats including INT4/8, FP8, and BF16; and 3) an accurate/approximate dual-mode bit-parallel MAC circuit (DMBP-MAC) designed to provide a tradeoff between computational accuracy and energy efficiency. A fabricated 28-nm 32-kB transpose SRAM CIM macro achieved average energy efficiency of 70.2–285.4 TOPS/W in INT4, 17.5–71.4 TOPS/W in INT8, 51.1–192.3 TFLOPS/W in FP8, and 12.8–48 TFLOPS/W in BF16.
Yiyang Yuan, Bingxin Zhang, Yiming Yang et al.· IEEE Journal of Solid-State...· 0 citations
We present PROTEUS, an 18 mm2 programmable general-purpose digital compute-in-memory (GP-DCIM) accelerator integrating 4 Mb resistive random access memory (RRAM) and 2.6 Mb tensor static random access memory (SRAM) with a 32-bit hierarchical DCIM instruction set architecture (ISA). PROTEUS features fine-grained 1-D matrix tiling and a reconfigurable DCIM datapath/pipeline for near-100% memory utilization, supporting INT8/INT16/FP8/FP16 DCIM computations. PROTEUS unifies SRAM/RRAM dataflows and embeds nonvolatile micro-programs in RRAM to enable rapid switching among prestored kernels without incurring off-chip instruction feeds or RRAM rewrites. Fabricated in 40 nm ultra-low power (ULP) CMOS with foundry RRAM, PROTEUS delivers 702 GOPS throughput, 6.4 TOPS/W energy efficiency, and 0.039 TOPS/mm2 compute density. It is validated on ResNet-20, BERT-Tiny, MobileViT, GraphSAGE, and Vision Mamba, demonstrating versatility across CNN, Transformer, hybrid CNN-Transformer, graph neural network (GNN), and state-space model (SSM) workloads.
Luqi Zheng, A. M. Bavani, Mufeng Chen et al.· IEEE Journal of Solid-State...· 0 citations
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Piecewise linear approximation (PLA) is pivotal for compressing time-series data under stringent error constraints. However, conventional PLA methods often struggle to reconcile the inherent conflict between aggressive compression ratios (CRs) and the preservation of complex local trends. In this article, we propose Tcm, a high-performance compression framework that achieves a synergistic balance between fidelity and efficiency. Unlike static approximation techniques, Tcm introduces a dynamic error thresholding strategy powered by a trend-aware simulated annealing (SA) optimizer, ensuring a global maximum error bound of < 1%. By integrating multimodal preprocessing—including wavelet denoising, seasonal-trend decomposition (STL)-support vector machine (TSVM) decomposition, and adaptive chunking—Tcm effectively harmonizes fine-grained precision with coarse-grained representation. Experimental evaluations on large-scale industrial datasets demonstrate that Tcm outperforms state-of-the-art benchmarks (e.g., Sim-Piece and Mix-Piece), delivering a 28.1% average improvement in CR and a 40% reduction in segment redundancy. Furthermore, Tcm exhibits superior robustness in high-volatility scenarios, such as financial forecasting and industrial sensing. By optimizing the “computation-for-transmission” tradeoff, Tcm provides a scalable and energy-efficient solution for real-time telemetry and edge computing applications.
Dong Chen, Wei-Jie Wang, Xianyou Zhu et al.· IEEE Internet of Things Jour...· 0 citations
This article investigates the dynamic multiobjective co-optimization problem in unmanned aerial vehicle (UAV)-assisted remote sensing systems, aiming to jointly optimize UAV placement, task scheduling strategies, and computing/communication resource allocation to minimize the system’s average processing latency and the total energy consumption of UAVs. Addressing the shortcomings of existing research, which often overlooks the computational capabilities of UAVs, optimizes only a single aspect, and fails to account for environmental dynamics, this work formulates the problem as a dynamic multiobjective optimization problem. A hybrid optimization framework named DSG, integrating swarm intelligence and evolutionary algorithms, is proposed. The framework first derives a closed-form optimal resource allocation solution for given deployment and scheduling strategies through theoretical analysis. It then employs an improved dynamic multiobjective evolutionary algorithm (DMOEA) to co-optimize UAV positions (continuous variables) and task scheduling (discrete variables). Experimental results demonstrate that DSG achieves significantly better normalized hypervolume performance than comparative algorithms across various system scales [number of UAVs, access points (APs), and sensors] while exhibiting good stability and scalability. This provides an effective solution for the efficient co-optimization of UAV-assisted edge computing in dynamic environments.
Bo Wang, Xiaoyun Qin, Zhifeng Zhang et al.· IEEE Internet of Things Jour...· 0 citations
Vehicular edge computing (VEC), a key enabler for the Internet of Things (IoT) in intelligent transportation, addresses onboard processing constraints through collaborative task offloading among vehicles, facilitating latency-sensitive applications such as autonomous driving. However, developing efficient offloading strategies remains particularly challenging in high-density vehicular networks, where intensive computational demands coexist with severely constrained intervehicle communication ranges due to signal blockage. To handle this, we propose M4O, a mobility-aware task offloading framework supporting multihop, multiuser, and multitask offloading optimization. M4O intelligently integrates vehicle mobility patterns and enables relay-assisted offloading to enhance system effectiveness and robustness. The framework employs a dual-algorithm approach: the advantage actor–critic (A2C) for indivisible tasks and the hybrid proximal policy optimization (H-PPO) for divisible tasks, both optimized to minimize the temporally coupled composite cost of time and resources. Extensive experiments demonstrate that the deep reinforcement learning (DRL)-based solutions of M4O deliver stable and efficient offloading strategies, outperforming existing benchmarks by significant margins in cost efficiency. Our code is available at https://github.com/Zhouym1028/M4O
Momiao Zhou, Yimin Zhou, Yanshi Sun et al.· IEEE Internet of Things Jour...· 0 citations
Edge devices capable of running artificial intelligence (AI) applications have seen a surge in demand for energy-efficient and high-throughput computation. In this study, a 22-nm edge–AI processor, incorporating an accelerator with error-free Booth-value-confined (BVC) multiprecision (MP) multiplier and near-memory computing (NMC), is introduced to accelerate neural networks (NNs). It has the following three major features. First, a BVC MP multiplier based on radix-8 Booth (R8B) is introduced to reduce computation complexity by prohibiting the “±3” cases and support error-free training on GPU without accuracy loss originating from the mismatch between training and deployment. A PE is built based on this multiplier for parallel computation with 82% power reduction and 70% area reduction. Second, the proposed NMC-friendly data flow supports efficient data reuse and hence reduces off-chip memory traffic. The data flow supports data reuse of up to 16 times, matching the number of PEs and enabling regular read and write patterns. Third, a hardware-aware layer-wise model deployment approach is proposed with a memory space contiguity-aware (MSCA) model reshape strategy, and a hardware-aware NN splitting and scheduling algorithm. The proposed MSCA strategy maximizes burst access, and the proposed algorithm achieves efficient computation with high data reuse and low memory access. This deployment approach can achieve a reduction in memory access latency of 16.6%–32.0%. Measurements on a 22-nm test chip demonstrate a peak power efficiency of 33.98 TOPS/W under synthetic full-PE-utilization conditions, while achieving 12.92–29.11 TOPS/W for end-to-end NN inference on DarkNet19, VGG16, ViT-Tiny, and ResNet34.
Quan Cheng, Longyang Lin, Mingqiang Huang et al.· IEEE Transactions on Very La...· 0 citations
Graph convolutional networks (GCNs) have demonstrated strong capability in modeling graph-structured data and have been widely adopted in various industrial applications. With the rapid growth of edge computing, designing GCN accelerators that maintain high performance under strict resource constraints has become increasingly important. This article presents SPP-GCN, a hardware–software co-optimized accelerator that significantly improves memory efficiency (ME) while maintaining competitive performance. SPP-GCN introduces four hardware–software co-optimization strategies—shuffle, z-merge, concatenation, and preplanning cache—to leverage software-side preprocessing and enhance the graph awareness of the hardware execution pipeline. These techniques effectively improve processing-element utilization and reduce on-chip memory footprint. Evaluated on both GCN and GraphSAGE models across multiple benchmark datasets, SPP-GCN achieves up to $86.9\times $ and $18.85\times $ latency reductions compared with CPU and GPU implementations, respectively. Compared with a prior lightweight accelerator, LW-GCN, SPP-GCN further reduces on-chip memory consumption by 58.5% while achieving up to $1.27\times $ higher relative performance (RP) under the adopted CE/RP-normalized comparison methodology. In addition, although several existing field-programmable gate array (FPGA) accelerators (e.g., BoostGCN, FP-GNN, and Graph-OPU) provide competitive latency, they require significantly larger on-chip memory resources. To better characterize performance density under resource constraints, we further introduce a ME metric that quantifies the RP achieved per unit of on-chip memory. Experimental results show that SPP-GCN consistently achieves the highest ME under the proposed ME metric among the evaluated FPGA-based GCN accelerators. These results demonstrate that the proposed hardware–software co-optimization framework effectively balances performance and resource utilization, making SPP-GCN particularly suitable for memory-constrained edge platforms.
Yi-Zhang Wu, Xiang-Yin Chen, Chen Yang· IEEE Transactions on Very La...· 0 citations
Mobile edge computing (MEC) has emerged as a promising paradigm to support latency-sensitive applications by deploying computing and storage resources closer to end users. Service caching at the network edge is an effective approach to further reduce response latency and improve quality of service (QoS). However, the increasing scale and dynamic nature of user requests pose significant challenges to efficient service caching and updating under limited edge resources and cost budgets. In this article, we investigate the joint optimization problem of service caching and dynamic updating in a cloud–edge–end collaborative architecture, with the objective of minimizing the average service access latency of users. We first construct a comprehensive system model that captures communication latency, service response delay, and the costs associated with service caching and updates. The problem is formulated as a nonlinear integer programming problem and addressed via a two-stage solution framework. Specifically, in the initial caching stage, we employ Lagrangian relaxation to reduce the high-dimensional knapsack problem and design an efficient algorithm integrated with Tabu Search. In the dynamic updating stage, we develop a Monte Carlo tree search (MCTS)-based algorithm enhanced by service popularity awareness, along with a novel service replacement strategy that considers user preference and service reliability. Extensive experiments under various system scales demonstrate that the proposed approach significantly outperforms state-of-the-art methods in terms of average service latency, cost budget satisfaction, and update efficiency.
Tianyang Zheng, Pengfei Yang, Kang Shen et al.· IEEE Internet of Things Jour...· 0 citations
Autonomous driving vehicles (ADVs) are transforming urban mobility with advanced sensors for real-time decision-making, promising safer and more efficient transportation. Despite recent advancements targeting accident reduction and efficiency improvement, challenges like sensor range limitations persist. Edge-assisted perception, facilitated by vehicle-to-everything (V2X) communications, addresses these limitations by sharing data among ADVs, enhancing accuracy in complex driving scenarios. However, this approach amplifies real-time computing challenges due to wireless communication-induced suspensions. This work presents a solution called MCS3 a suspension-aware mixed-criticality system (MCS) for edge-assisted computing. MCS3 addresses real-time challenges through a hardware–software co-design, introducing a MCS3-bridge for monitoring peripheral traffic with a dual-mode scheduler. MCS3 is implemented on the AMD Virtex VC709 FPGA and examined using comprehensive metrics. The experimental results show that MCS3 significantly improves the system-wide real-time performance with light overhead on both hardware and software.
Zhe Jiang, Xiaoxuan Wang, Zhenghui Guo et al.· IEEE Transactions on Compute...· 0 citations
Multiaccess edge computing (MEC) has emerged as a key paradigm to empower resource-constrained edge devices through task offloading. However, dynamically fluctuating user preferences regarding latency and energy tradeoffs severely complicate the task scheduling and resource allocation, while existing methods struggle to accommodate this variability. To address this, we first formulate the dynamic-weight task offloading challenge as a nonconvex, nondeterministic polynomial-time (NP) hard multiobjective optimization problem (MOOP). We then propose a dynamic multiobjective task offloading framework built upon an enhanced proximal policy optimization algorithm to tackle this MOOP, namely DMT-PPO, which incorporates a dynamic reward structure and preference-aware subnetworks to effectively model user preferences and adapt to varying weight conditions. By introducing a discrete-continuous hybrid action space, DMT-PPO achieves the joint optimization across server selection, offloading decision, and computing provisioning. Moreover, DMT-PPO leverages a domain-based transfer learning (TL) paradigm coupled with an edge caching mechanism to accelerate both training and decision processes, enabling fine-grained coordination among heterogeneous task, device, and edge server settings. Extensive experiments demonstrate our framework’s superiority in dynamic environments, achieving up to 12.5% energy savings and a 10.6% reduction in task completion time, alongside a $3.5\times $ improvement in training efficiency compared to state-of-the-art baselines like Hybrid-PPO.
Honggang Yuan, Yuxiang Deng, Xiao Du et al.· IEEE Internet of Things Jour...· 0 citations
What if pathology foundation models could do more with less? GigaPath-Flash and GigaTIME-Flash cut computational demands while maintaining strong performance, opening the door to larger studies and broader exploration. The post GigaPath-Flash and GigaTIME-Flash: Toward population-scale discovery with efficient pathology foundation models appeared first on Microsoft Research.
MIT News · Artificial Intelligence· news.mit.eduAug 31, 2026
With millions of users across the world, Julia has been used to conduct cutting-edge research and to design new drugs, jet engines, heat pumps, and more.
MIT News · Artificial Intelligence· news.mit.eduAug 27, 2026
A new machine-learning framework aims to improve the success rate of computational protein design while moving away from results that reproduce sequences found in nature.
