Lessons from the Hardware Hacking Competitions: Verification Techniques, Findings, and Insights
TL;DR
A multi-strategy vulnerability analysis methodology is presented, combining simulation-based verification, formal verification, lint analysis, Large Language Model-assisted bug detection, and coverage-guided hybrid fuzzing to derive practical lessons for pre-silicon security verification.
Abstract
Hardware hacking competitions have emerged as practical platforms for evaluating security weaknesses in complex System-on-Chip (SoC) designs while promoting security-aware verification and tool development. This paper presents a systematic study of SoC security verification through open-box hardware hacking competitions, focusing on practical vulnerability analysis strategies, observed findings, and lessons for security-aware verification. We present a multi-strategy vulnerability analysis methodology, combining simulation-based verification, formal verification, lint analysis, Large Language Model (LLM)-assisted bug detection, and coverage-guided hybrid fuzzing. Representative vulnerability findings are analyzed to illustrate how different techniques expose complementary classes of security flaws, and we derive practical lessons for pre-silicon security verification. Finally, we discuss how competition benchmarks can support the reproducible evaluation of emerging hardware security techniques and guide future security-aware EDA research.