Design of Analog SNNs with 4-Bit Programmable Synapses Using Molecular FETs

Abstract

Spiking neural networks (SNNs) are well suited for low-power inference, particularly when implemented in analog hardware. However, in analog SNNs, synaptic elements dominate area and strongly influence scalability and robustness, making efficient synapse design a key challenge. Non-volatile devices are therefore attractive for synaptic weight storage, and molecular field-effect transistors (FETs) offer compact, persistent switching behavior suitable for analog integration. This work proposes a novel programmable synapse architecture constructed from binary molecular FET devices, where multi-bit weights are realized architecturally using power-of-two-scaled gate geometries. A hardware-aware training and mapping framework is developed and validated using SPICE-level circuit simulations alongside system-level PyTorch models of the proposed synapse. We further analyze the robustness of the proposed architecture to synaptic non-idealities arising from finite on-off ratio. These results indicate that architecturally constructed programmable synapses from simple binary molecular devices provide a robust and scalable approach for analog SNN hardware.